AN1602 Freescale Semiconductor / Motorola, AN1602 Datasheet - Page 5

• Manufacturer Part Number: AN1602
• Description: AN1602 Application Note: Dual-Band PA Application w/DECT Capability Using Std RFICs
• Manufacturer: Freescale Semiconductor / Motorola

BOARD DESCRIPTION
DC and Control Section
placement for 3.6 V application is shown in Figure 3 and the
placement for the 4.8 V board is shown in Figure 17.
voltage is much higher than this value, there is a clamping
current in this diode, which may generate some spurious
signals on the negative supply.
power supply line of the MC33169 (R19, C32). When 3.6 V
battery is at low voltage (3.0 V), there is a 0.2 V drop on the
U3 supply line. This point is much more critical in the 4.8 V
application where R19 resistor provides a 1.0 V drop in this
case, which allows the MC33169 to work down to 4.0 V
V
MRFIC0917 is in ON–state, and MRFIC1817 is in OFF–state
(MRFIC0913 and MRFIC1818 respectively for the 4.8 V
application). MRFIC0917 (MRFIC0913) has an internal
MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
BATT
Input pins available on the DC connector are V
The output pins on the DC connector are ENSWT (optional
The negative voltage generator and control are organized
C22, C23 (1.0
C19, C20 are used for voltage doubler and tripler, which will
CR1 diode, C21, C25, C26 allow negative voltage detection
R8 (470
ENGSM pin which is compatible with CMOS logic, is biased
voltage), V
negative voltage generator), ENGSM (selects the RF path),
V
supply).
control voltage for a RF power switch), VGDECT/VCDCS
(gate bias voltage for DCS1800 PA), VCGSM (gate bias
voltage for GSM PA), V
Figure 4 shows an application schematic for a 3.6 V part
while Figure 18 shows an application schematic for the 4.8 V
part.
around Q1, Q2, Q3, Q4 and U3.
oscillator at 100 kHz. This value is not critical and could be
decreased to 220 nF.
allow to drive the NMOS transistor (Q1).
and filtering.
which could modulate Q1 gate and then be converted
beside the carrier. The negative voltage is regulated with an
internal zener diode.
by V
operates as a simple inverter and provides the ENSWT
signal and drives Q3 and Q4. Note that Q2 is a self–biased
transistor (MMUN2112LT1).
The demonstration board layout and component
As MC33169 is able to operate at 2.7 V, when the battery
To avoid this issue, a RC filter cell has been inserted on the
When ENGSM = 0 V then VCDCS = –4.0 V, VCGSM = 0 V,
RAMP
.
REG
(RF power control) and V
(regulated 3.0 V) and V
) gives additional filtering of 100 kHz spurious
REG
(regulated 3.0 V supply), IDLE (enable the
F) are used for internal charge pump
D
(drain voltage for both PA’s).
Freescale Semiconductor, Inc.
SS
For More Information On This Product,
(regulated –4.0 V). Q2
REG
(regulated 3.0 V
Go to: www.freescale.com
BATT
(battery
resistor bridge connected between VCGSM and V
to be at this nominal quiescent current, about 800 mA to 1200
mA, (500 mA to 900 mA for the 4.8 V application) when
VCGSM = 0 V. This biasing point can also be fine tuned by
adjusting R2 and R3 resistors which impact first and second
stage amplifier current respectively.
VCGSM = –4.0 V, MRFIC0917 is in OFF–state, and
MRFIC1817 is in ON–state. A difference between
MRFIC0917 and MRFIC1817 is that the DCS amplifier does
not have an internal resistor bridge, but does have a single
biasing resistor which supplies the three stages. For this
reason, –2.0 V is required on VCDCS to bias the amplifier at
its nominal quiescent current.
supplied to the gates. The pinch–off voltage of the GaAs
transistors used is –2.5 V, so the current consumption is then
lower than 0.5 mA. The user needs to keep the drive level low
enough at the disabled PA input, otherwise it may operate as
a class C amplifier and conduction may occur. This maximum
drive level is about 5.0 dBm for MRFIC0917/MRFIC0913 and
3.0 dBm for MRFIC1817/MRFIC1818 as well. This is an
important point which needs to be highlighted.
path needs to not exceed 3.0 dBm; and when the DCS mode
is selected, RF drive on the GSM path needs to not exceed
5.0 dBm.
amplifiers are supplied together (Otherwise it would have
been necessary to use two different N–MOS transistors).
RF SECTION
GSM Path
cell which has been tuned at rated power. Interstage
matching has been optimized by implementing (as shown in
Figure 3) C10 and C12 decoupling capacitors on two
microstrip lines. 33 pF in 0603 size has been found optimum
for GSM.
filter using a 30
L4 inductor allows for optimized efficiency while impacting
harmonic impedances in the output transistor plane.
However, the inductor needs to be a high–Q part with a
high–DC maximum current (a Coilcraft Microspring Series
has been implemented). This parallel inductor can also be
realized with a 20 mm microstrip line. In this application the
best surface solution has been selected. In the 4.8 V
application, when efficiency is not critical those two parts can
be avoided. The loss of efficiency will be then 3 to 4%. (For
typical performances see Table 3/Table 4 in the Appendix).
Typical gain and return loss at rated power are given in Figure
5 for GSM path (Figure 18 for the 4.8 V application).
When ENGSM = 3.0 V then VCDCS = –2.0 V,
To put the power amplifier in the OFF–state, –4.0 V are
When the GSM mode is selected, RF drive on the DCS
During all the sequence, drain pins of both power
The input match is a shunt C (C9) series L (L3), low–pass
The output matching is realized with a one–cell, low–pass
microstrip line and C13 + C14 capacitors.
SS
, in order
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