AN2008 Motorola / Freescale Semiconductor, AN2008 Datasheet - Page 8

• Manufacturer Part Number: AN2008
• Description: Evaluating ColdFire in a 68K Target System: MCF5307 to MC68EC020 Gateway Reference Design
• Manufacturer: Motorola / Freescale Semiconductor

Alternatively, if both the transfer type and modifier pins are all de-asserted, the transfer modifier pins carry
the interrupt level being acknowledged. Thus in this case, interrupt level 7 would be acknowledged.
The bus is granted to the target hardware when the bus request from the target is asserted and the bus is not
already granted to the MCF5307 microprocessor.
Similarly, the bus is granted to the MCF5307 microprocessor as soon as possible after receipt of a valid bus
request signal. The bus will be granted to the MCF5307 when either the MCF5307 has requested the bus or
when the target hardware is not requesting the bus and the bus is being driven.
1.2.5.2 PAL Control Equations—U11
The transfer acknowledge bus sizing control signals are controlled by PAL U11.
The MC68EC020 can dynamically interpret the port size of the addressed device during each bus cycle.
Unfortunately, the MCF5307 Microprocessor cannot perform this type of dynamic bus sizing. When the
MCF5307 is the bus master, however, it can use the size pins (SIZ[1:0]) to indicate the requested transfer
size for bus cycle encoding. When the MC68EC020 is the bus master the size pins will be inputs.
The SIZ0 pin on the MCF5307 Microprocessor is asserted when the DSACK0 signal is not asserted and the
DSACK1 signal is asserted. Similarly, the SIZ1 signal is asserted when the DSACK1 signal is not asserted
and the DSACK0 signal is asserted. (The DASCK0/1 signals on the MC68EC020 are logically opposite to
the SIZ0/1 signals on the MCF5307).
PAL output pins 14 and 15 are connected to hardware test pads. Example logic for coding PAL output pin
14 has been given in Appendix B. The example code asserts signal “SPARE” (Pin 14) when both the
DSACK signals are asserted indicating that the Data bus port size is encoded for 32 bits. (The NC on pin 15
could be coded in a similar fashion for other user specific functions.)
If the target device is driving the bus and asserts any of the DSACK signals then the transfer acknowledge
signal on the MCF5307 is asserted. Note that this control line requires a pull-up resistance of 1Kohms to
ensure a fast negation of this signal, which in turn prevents false cycles on the bus. The SIZ0 and SIZ1
signals generated by the PAL are tied high internally to prevent glitches during reset. The TA signal is set
to default to a data bus size of 32 bits on reset using the “SPARE” control line and DSACK0 / 1 signals.
Appendix B illustrates the corresponding set of PAL control equations for generating the TA bus sizing and
test pad control signals.
1.2.6 Test Points, Decoupling and Pull-Up Resistors
The schematic shown in Appendix I detail the key signals that can be accessed through test points positioned
throughout the board to aid debugging. The basic signals that are accessible are /TS, /AS, /CS5, /TA, R/W,
GND and VDD (3.3V).
Also listed on this schematic page are the signals that must be pulled-up to a high logic level to avoid false
signaling. Each signal that requires a pull-up is tied to 3.3V using a 4.7Kohm resistor.
Jumper JP4 on the schematic selects BDM debug operation or JTAG operation of the test module on the
MCF5307 microprocessor. If the jumper is placed in position 2 / 3, BDM operation will be selected.
Similarly, if the jumper is placed in position 1 / 2, the Gateway board will select JTAG operation. This signal
is then fed into the MCF5307 microprocessor on test mode pin MTMOD0.
The schematic also shows the decoupling capacitors that need to be connected to the power and ground pins
of all on-board chips to minimise the effects of noise in the system. Note the use of both 0.1uF and 1nF
capacitors to inhibit both low and high frequency noise in the system.
MC68EC020 PGA—MCF5307FT, Gateway Reference Design
Appendix A illustrates all of the relevant control equations and simulation setups for coding PAL U10.
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MCF5307 to MC68EC020 Gateway Reference Design