AN2074 Freescale Semiconductor / Motorola, AN2074 Datasheet - Page 2

• Manufacturer Part Number: AN2074
• Description: DSP56300 JTAG Examples
• Manufacturer: Freescale Semiconductor / Motorola

2
As noted above, the IEEE 1149.1 test structures include several data registers. The architecture also
requires an instruction register. All of the registers are accessed serially through the TAP, and, when
selected, connect between the
controller, which is a state machine. The state is changed by the Test Mode Select (
conjunction with the Test Clock (
After reset, the Instruction Register is loaded with the IDCODE instruction, and the ID Register is the
selected data register. You can perform a data scan to read the device information. For other operations,
the TAP programming sequence must begin with a scan into the Instruction Register to specify the
appropriate data register. After an Instruction Register scan, subsequent scans are through the specified
data register and may involve several scans of data into or through it (in the case of OnCE programming).
Write operations pass data into the registers from
through
•
•
•
•
Input Pins
Bypass Register
Device ID Register
Boundary Scan Register
OnCE Registers through the OnCE Command Register (OCR)
TDO
TMS
TCK
TDO
TDI
. Figure 2 shows the DSP56300 family implementation of the IEEE 1149.1 test architecture.
TAP
Freescale Semiconductor, Inc.
TDI
For More Information On This Product,
Figure 2. Boundary-Scan Architecture
TCK
and
DSP56300 JTAG Examples
Boundary-Scan Register
). In the DSP56300 family, the data registers include the following:
Instruction
TDO
Registers
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Register
Register
Register
Bypass
OnCE
ID
Core Logic
pins. Access to the registers is controlled by the TAP
TDI
. Read operations pass data out of the registers
TMS
Output Pins
) signal in