ACS709 Allegro MicroSystems, Inc., ACS709 Datasheet - Page 12

• Manufacturer Part Number: ACS709
• Description: High Bandwidth, Fast Fault Response Current Sensor Ic In Thermally Enhanced Package
• Manufacturer: Allegro MicroSystems, Inc.

ACS709
Overcurrent Fault Operation
The primary concern with high-speed fault detection is that noise
may cause false tripping. Various applications have or need to
be able to ignore certain faults that are due to switching noise
or other parasitic phenomena, which are application dependant.
The problem with simply trying to filter out this noise up front is
that in high-speed applications, with asymmetric noise, the act of
filtering introduces an error into the measurement. To get around
this issue, and allow the user to prevent the fault signal from
being latched by noise, a circuit was designed to slew the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯
pin voltage based on the value of the capacitor from that pin to
ground. Once the voltage on the pin falls below 2 V, as estab-
lished by an internal reference, the fault output is latched and
pulled to ground quickly with an internal N-channel MOSFET.
Fault Walk-through
The following walk-through references various sections and
attributes in the figure below. This figure shows different
fault set/reset scenarios and how they relate to the voltages on
the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin, FAULT_EN pin, and the internal Overcurrent
(OC) Fault node, which is invisible to the customer.
1. Because the device is enabled (FAULT_EN is high) and there is
an OC fault condition, the device ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin starts discharging.
(Active High)
FAULT_EN
Condition
OC Fault
(Output)
FAULT
(Input)
V
2 V
0 V
CC
1
4
2
High Bandwidth, Fast Fault Response Current Sensor IC
3
Functional Description
6
Time
2. When the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin voltage reaches approximately 2 V, the
3. When the FAULT_EN pin is brought low, the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin starts
4. The slope, and thus the delay, on the fault is controlled by the
5.
fault is latched, and an internal NMOS device pulls the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯
pin voltage to approximately 0 V. The rate at which the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯
pin slews downward (see [4] in the figure) is dependent on the
external capacitor, C
resetting if no OC Fault condition exists. The internal NMOS
pull-down turns off and an internal PMOS pull-up turns on (see
[7] if the OC Fault condition still exists).
capacitor, C
portion of the fault (when the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin is between V
2 V), there is a 3 mA constant current sink, which discharges
C
where V
the OC fault condition cleared. Because of this, the fixed 3 mA
current sink turns off, and the internal PMOS pull-up turns on to
recharge C
1
OC
The ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin did not reach the 2 V latch point before
. The length of the fault delay, t, is equal to:
4
5
CC
6
In Thermally Enhanced Package
OC
is the device power supply voltage.
OC
through the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin.
, placed on the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin to ground. During this
t =
1
C
OC
OC
, on the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin.
( V
3 mA
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
4
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
CC
– 2 V )
2
7
6
8
4
CC
2
and
(1)
12