CY2280 Cypress Semiconductor, CY2280 Datasheet
CY2280
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CY2280 Summary of contents
Page 1
... The device can be run without spread spectrum when the SEL_SS input is deasserted. The percentage of spreading is EPROM-programmable to optimize EMI-reduction. The CY2280 has power-down, CPU stop, and PCI stop pins for power management control. The signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. ...
Page 2
... SS 42 RESERVED DDCPU 9 40 CPUCLK0 10 39 CPUCLK1 DDCPU 13 36 CPUCLK2 14 35 CPUCLK3 PCI_STOP 19 30 CPU_STOP 20 29 PWR_DWN 21 28 SEL_SS 22 27 SEL0 23 26 SEL1 CY2280-11S 24 25 SEL100 CY2280-21S Page ...
Page 3
... CPUCLK PCICLK Low Low Low Low Low Running Running Low Running Running CY2280 REF APIC USBCLK Hi-Z Hi-Z Hi-Z 14.318 MHz 14.318 MHz 48 MHz 14.318 MHz 14.318 MHz 48 MHz 14.318 MHz 14.318 MHz 48 MHz 14.318 MHz 14.318 MHz 48 MHz ...
Page 4
... Loaded Outputs, CPU = 66.6 MHz DDCPU 2.625V Loaded Outputs, CPU = 100 MHz DDCPU 3.465V Loaded Outputs Current draw in power-down state CY2280 pins tied together) DD Min. Max. Unit 3.135 3.465 2.375 2.625 2.375 2.625 ...
Page 5
... Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.25V for 2.5V clocks Measured at 1.25V Measured at 1.25V Measured at 1.5V CPU, PCI clock stabilization from power-up = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V. DD CY2280 Min. Max. Unit Min. Typ. Max. Unit -1,-11S, 1.0 4.0 V/ns -21S -1,-11S, 1 ...
Page 6
... All Outputs Rise/Fall Time OUTPUT CPU-CPU Clock Skew CPUCLK CPUCLK t 5 CPU-PCI Clock Skew CPUCLK PCICLK t 6 PCI-PCI Clock Skew PCICLK PCICLK t 7 CPU-APIC Clock Skew (-21S only) CPUCLK APIC t 8 Document #: 38-07207 Rev CY2280 Page ...
Page 7
... PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Document #: 38-07207 Rev. *A CY2280 Page ...
Page 8
... Modulation Frequency Down Spread Margin at the Fundamental Frequency Down Spread Margin at the Fundamental Frequency Document #: 38-07207 Rev. *A Spread Spectrum Disabled Frequency (MHz) Configuration Outputs All (except -1) -11S CPU, PCI -21S CPU, PCI, APIC CY2280 Min. Max. Unit 30.0 33.0 kHz 0.0 –0.6 % 0.0 –0.6 % Page ...
Page 9
... If a Ferrite Bead is used F–22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Document #: 38-07207 Rev. *A from the clock generator V island. Ensure that the Ferrite Bead offers DD DD CY2280 of LOAD Page ...
Page 10
... Notes: Each supply pin must have an individual decoupling capacitor. All capacitors must be placed as close to the pins as is possible. Package Type O48 48-Pin SSOP O48 48-Pin SSOP O48 48-Pin SSOP CY2280 OUTPUTS C LOAD Operating Range Commercial Commercial Commercial CY2280 Page ...
Page 11
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-Lead Shrunk Small Outline Package O48 CY2280 51-85061-B Page ...
Page 12
... Revision History Document Title: CY2280 100-MHz Pentium PCs Document Number: 38-07207 Issue REV. ECN NO. Date ** 111721 12/16/01 *A 121842 12/14/02 Document #: 38-07207 Rev. *A ® II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop Orig. of Change Description of Change DSG Change from Spec number: 38-00694 to 38-07207 RBI ...