IDT72221L25JI IDT, Integrated Device Technology Inc, IDT72221L25JI Datasheet - Page 8
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IDT72221L25JI
Manufacturer Part Number
IDT72221L25JI
Description
IC FIFO SYNC 1KX9 25NS 32PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet
1.IDT72211L10JG.pdf
(14 pages)
Specifications of IDT72221L25JI
Function
Synchronous
Memory Size
9K (1K x 9)
Data Rate
40MHz
Access Time
25ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Configuration
Dual
Density
9Kb
Access Time (max)
15ns
Word Size
9b
Organization
1Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
PLCC
Clock Freq (max)
40MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72221L25JI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72221L25JI
Manufacturer:
IDT11
Quantity:
662
Company:
Part Number:
IDT72221L25JI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72221L25JI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
©
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable
2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
NOTE:
1. t
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
REN1, REN2
(If Applicable)
flag offset registers.
and the rising edge of WCLK is less than t
WEN2/LD
SKEW1
EF, PAE
FF, PAF
Q
WEN1
0
is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK
D
WEN2/
- Q
WCLK
REN1,
WEN1
RCLK
REN2
RS
0
- D
8
FF
(1)
8
t
SKEW1
(1)
SKEW
1, then FF may not change state until the next WCLK edge.
t
t
t
RSF
RSF
t
CLKH
RSF
t
WFF
t
RS
DATA IN VALID
t
t
t
Figure 5. Write Cycle Timing
RSS
RSS
RSS
Figure 4. Reset Timing
t
CLK
8
t
CLKL
t
t
ENS
ENS
t
DS
t
t
t
DH
ENH
ENH
t
t
t
RSR
RSR
RSR
t
WFF
OE = 1
COMMERCIAL AND INDUSTRIAL
OE = 0
NO OPERATION
NO OPERATION
(2)
TEMPERATURE RANGES
OCTOBER 22, 2008
2655 drw 07
2655 drw 06