CY24239 Cypress Semiconductor, CY24239 Datasheet - Page 2

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CY24239

Manufacturer Part Number
CY24239
Description
Spread Spectrum Frequency Timing Generator
Manufacturer
Cypress Semiconductor
Datasheet

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Pin Definitions
Document #: 38-07038 Rev. **
CPU1:2
CPU_F
PCI1:5
PCI0/FS3
PCI_F/MODE
CLK_STOP#
IOAPIC_F
IOAPIC0
48MHz/FS1
24MHz/FS0
REF1/FS2
REF0
(PCI_STOP#)
SDRAMIN
SDRAM0:16
SCLK
SDATA
X1
X2
VDDQ3
GND
Pin Name
11, 12, 13, 14,
44, 43, 41, 40,
39, 38, 36, 35,
22, 21, 19, 18,
33, 32, 25, 24,
31, 37, 45, 50,
34, 42, 48, 53
4, 10, 23, 26,
1, 7, 15, 20,
Pin No.
51, 49
52
16
47
54
55
29
30
17
46
28
27
56
9
8
2
3
5
6
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
G
P
I
I
I
I
I
CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. These outputs are affected by the CLK_STOP# input.
Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. This output is not affected by the CLK_STOP# input.
PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. These outputs are affected by the PCI_STOP# input.
PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs
or through serial input interface, see Table 2 and Table 6. This output is affected by the
PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and
PCI outputs.
Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. This output is not affected by the PCI_STOP# input.
When an input, selects function of pin 3 as described in Table 1.
CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after com-
pleting a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected outputs
start beginning with a full clock cycle (2–3 CPU clock latency).
Free-running IOAPIC Output: This output is a buffered version of the reference input
which is not affected by the CPU_STOP# logic input. Its swing is set by voltage applied
to VDDQ3.
IOAPIC Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set
by voltage applied to VDDQ3. This output is disabled when CLK_STOP# is set LOW.
48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this
output can be used as the reference for the Universal Serial Bus. Upon power-up, FS1
input will be latched, setting output frequencies as described in Table 2.
24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this
output can be used as the clock input for a Super I/O chip. Upon power up, FS0 input
will be latched, setting output frequencies as described in Table 2.
Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2
input will be latched, setting output frequencies as described in Table 2.
Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin.
The PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to
remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of
PCI_F. Its effects take place on the next PCI_F clock cycle. As an output, this pin provides
a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins
(14.318 MHz).
Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs
(SDRAM0:16).
Buffered Outputs: These seventeen dedicated outputs provide copies of the signal
provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated
when CLK_STOP# input is set LOW.
Clock pin for SMBus circuitry.
Data pin for SMBus circuitry.
Crystal Connection or External Reference Frequency Input: This pin has dual func-
tions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
Power Connection: Power supply for core logic, PLL circuitry, SDRAM output buffers,
PCI output buffers, reference output buffers and 48-MHz/24-MHz output buffers. Con-
nect to 3.3V.
Ground Connections: Connect all ground pins to the common system ground plane.
Pin Description
CY24239
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