CY26114 Cypress Semiconductor, CY26114 Datasheet
CY26114
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CY26114 Summary of contents
Page 1
... Pin Configurations 100MHz 16-pin TSSOP 100MHz 1 XIN 50MHz 2 VDD AVDD 3 25/33/50/66MHz FS0 (frequency selectable) 4 AVSS 5 VSSL 6 7 LCLK1 8 LCLK2 • San Jose • CA 95134 • Revised December 14, 2002 CY26114 XOUT 16 15 CLK4 14 CLK3 13 VSS 12 N/C 11 VDDL 10 FS1 9 N/C 408-943-2600 ...
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... Min. –0.5 Digital Inputs DDL SS 2 Description Min. 3.0 2.375 0 0.05 Level DDL Level DDL Max. 7.0 7.0 125 – 0 0.3 DD – 0 0.3 DD – 0.3 V +0.3 DDL Typ. Max. 3.3 3.6 2.5 2.625 500 CY26114 Unit V V ° Unit V V °C pF MHz ms Page ...
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... Figure 1. Duty Cycle Definitions t2/t1 80% CLK 20% Figure 2. Rise Time and Fall Time Definitions. Min. Typ 0.7 Min. Typ 0.8 1.4 0.6 1.2 0.8 1.4 0.6 1.2 CY26114 Max. Unit VDD 0.3 VDD Max. Unit 55 % V/ns V/ns V/ns V/ns 250 ps 200 Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CLK out C OUTPUTS LOAD GND Package Type Operating Range 16-Pin TSSOP Commercial CY26114 Operating Voltage 3.3V Page ...
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... Document Title: CY26114 One-PLL Clock Generator Document Number: 38-07098 REV. ECN NO. ** 107333 *A 121867 www.DataSheet4U.com Document #: 38-07098 Rev. *A Issue Date Orig. of Change 08/28/01 CKN 12/14/02 RBI CY26114 Description of Change New Data Sheet Power up requirements added to Operating Condi- tions Information Page ...