CY28301 Cypress Semiconductor, CY28301 Datasheet - Page 12

• Manufacturer Part Number: CY28301
• Description: Frequency Generator for Intel Integrated Chipset
• Manufacturer: Cypress Semiconductor

AC Electrical Characteristics
Document #: 38-07011 Rev. *C
CPUCLK
T
T
T
T
T
SDRAM
T
T
T
T
T
APIC
T
T
T
T
T
3V66
T
T
T
T
T
PCI
T
T
T
T
T
tp
tp
t
Notes:
Parameter
stable
4.
5.
6.
7.
8.
Period
HIGH
LOW
RISE
FALL
Period
HIGH
LOW
RISE
FALL
Period
HIGH
LOW
RISE
FALL
Period
HIGH
LOW
RISE
FALL
Period
HIGH
LOW
RISE
FALL
ZL
LZ
, tp
, tp
Period, jitter, offset, and skew measured on the rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
The time specified is measured from when V
and operating within specifications.
T
T
T
RISE
HIGH
LOW
ZH
ZH
and T
is measured at 0.4V for all outputs.
is measured at 2.0V for 2.5V outputs, and 2.4V for 3.3V outputs.
Host/CPUCLK Period
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
SDRAM CLK Period
SDRAM CLK High Time
SDRAM CLK Low Time
SDRAM CLK Rise Time
SDRAM CLK Fall Time
APIC CLK Period
APIC CLK High Time
APIC CLK Low Time
APIC CLK Rise Time
APIC CLK Fall Time
3V66 CLK Period
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
PCI CLK Period
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
Output Enable Delay (All outputs)
Output Disable Delay
(All outputs)
All Clock Stabilization from
Power-Up
FALL
are measured as transitions through the threshold region V
Description
[2]
DDQ3
(
T
A
achieves its nominal operating level (typical condition V
= 0°C to +70°C, V
66.6-MHz Host
Min.
15.0
10.0
60.0
25.5
25.3
15.0
5.25
5.05
30.0
12.0
12.0
5.2
5.0
0.4
0.4
3.0
2.8
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
1.0
1.0
Max.
15.5
10.5
64.0
16.0
10.0
10.0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.6
1.6
1.6
1.6
1.6
1.6
2.0
2.0
2.0
2.0
3
DDQ3
ol
= 0.4V and V
= 3.3V ±5%, V
25.30
100-MHz Host
Min.
10.0
25.5
15.0
5.25
5.05
30.0
12.0
12.0
10.0
60.0
3.0
2.8
0.4
0.4
3.0
2.8
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
1.0
1.0
oh
= 2.0V (1 mA) JEDEC specification.
Max.
10.5
10.5
16.0
10.0
10.0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.6
1.6
1.6
1.6
1.6
1.6
2.0
2.0
2.0
2.0
3
DDQ2
DDQ3
= 2.5V ±5% f
25.30
Min.
1.87
1.67
10.0
60.0
25.5
15.0
5.25
5.05
30.0
12.0
12.0
133-MHz Host
7.5
0.4
0.4
3.0
2.8
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
1.0
1.0
= 3.3V) until the frequency output is stable
Max.
XTL
10.5
64.0
16.0
10.0
10.0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
8.0
1.6
1.6
1.6
1.6
1.6
1.6
2.0
2.0
2.0
2.0
3
= 14.31818 MHz)
Unit
CY28301
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 12 of 15
5
6
4, 8
5
6
4, 7
5
6
4
6
4
5
6
4
5
Notes