CY28341 Cypress Semiconductor, CY28341 Datasheet - Page 18

• Manufacturer Part Number: CY28341
• Description: Universal Single-Chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07367 Rev. *A
Table 10. Signal Loading Table
For Differential CPU Output Signals (with P4 Processor SELP4_K7= 1)
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
Table 11. Lumped Test Load Configuration
Note:
32. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), the same
Component 0.7V Amplitude Value 1.0V Amplitude Value
REF (0:1), 48MHz (USB), 24_48MHz
AGP(0:2), SDRAM (0:11)
PCI_F(0:5)
DDRT/C (0:5), FBOUT
CPUT/C
CPUOD_T/C
CPUCS_T/C
R
R
R
R
C
LA1
LB1
tA1
tB1
LA
length transmission line to the other signal of the pair (e.g., AGP) should be added.
T
R
R
PCB
, R
, R
, R
, R
, C
ref
D
tA2
LA2
LB2
tB2
LB
475
MULTSEL
3” 50 Z
CPUT#
49.9
w/mult0 = 1
2 pF
33
CPUT
0
R
ref
R
R
Clock Name
tA1
tA2
221 w/mult0 = 0
3” 50 Z
470
2 pF
63
33
0
R
R
T
T
LA1
LA2
PCB
PCB
Figure 10.
R
R
LB1
LB2
Group Timing Relationships and Tolerances
t
t
CSAGP
AP
R
CPUCS to
AGP
AGP to
PCI
D
R
R
tB2
tB1
Offset (ps) Tolerance (ps) Conditions
1,250
750
C
C
CLK Measurement Point
CLK Measurement Point
LA
LB
Max Load (in pF)
See Figure 10
See Figure 8
See Figure 9
500
500
20
30
30
CY28341
Page 18 of 21
AGP Leads
CPUCS
Leads
[32]