CY28343 Cypress Semiconductor, CY28343 Datasheet
CY28343
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CY28343 Summary of contents
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... SSOP package OFF Active 2.5V 2.5V Compatible Compatible Active OFF OFF 3.3V Pin Configuration VDD_2.5V FBOUT_DDR DDRT(0:5) DDRC(0:5) VDD_3.3V FBOUT_SDR SDRAM (0:12) • 3901 North First Street • CY28343 FBOUT_DDR FBIN_SDR FBOUT_SDR Active OFF 2.5V Compatible OFF Active 3.3V Compatible Compatible [ SELDDR_SDR#* VDD_3. FBIN_DDR* SDRAM0 3 ...
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... For these applications the CY28343 offers single-end input as a PLL reference. The CY28343 then can lock onto the reference and translate with near zero to low-skew outputs. For normal operation, the ex- ternal feedback input, FBIN_DDR and FBIN_SDR, are con- ...
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... Read 29 Acknowledge from slave 30:37 Byte count from slave – 8 bits 38 Acknowledge 39:46 Data byte from slave –8 bits 47 Acknowledge 48:55 Data byte from slave – 8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop CY28343 Page ...
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... Command Code – 8 bits'1xxxxxxx' stands for byte operationbit[6:0] of the command code rep- resents the offset of the byte to be accessed 19 Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits 28 Read 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not Acknowledge 39 stop [4] Description [4] Description CY28343 Page ...
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... SDRAM9 Enable Output disabled asynchronously in a low state SDRAM8 Enable Output disabled asynchronously in a low state Byte 3: Silicon Register (Read Only) Bit @Pup Pin # 7 1 Vendor ID 1000 Cypress Revision Document #: 38-07369 Rev. *A [4] Description Description CY28343 Page ...
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... Typ. Max. 1.0 2.2 –0.3 0.8 –0.3 0.7 2 0 0.3 DD –10 10 235 300 4 Min. Typ. Max. 99 170 1.5 1.0 2 125 200 150 1.1 V – 0 /2) – 0 / CY28343 Unit Unit MHz % % ms V/ Page ...
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... VDD_3.3V = 3.3V ±5% 100 MHz, 133 MHz @133 MHz @133 MHz [11] [11] [11] 1.25V /1.5V 1.25V /1 large num ber o f sam ples Figure 1. Phase Error CY28343 Min Typ Max 99 133 0.4 1 200 400 200 1.1 V – 0.4 ...
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... Figure 4. Differential Signal Using Direct Terminal Resistor Document #: 38-07369 Rev Figure 2. Output Skew Figure 3. Cycle-to-Cycle Jitter T PCB 120 T PCB CY28343 Measurement Point 2 pF Measurement Point 2 pF Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Type 48-Lead Shrunk Small Outline Package O48 CY28343 Product Flow Commercial Commercial ...
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... Document Title:CY28343 Zero Delay SDR/DDR Clock Buffer Document #: 38-07369 Issue Rev. ECN No. Date ** 116671 08/22/02 *A 122909 12/26/02 Document #: 38-07369 Rev. *A Orig. of Change DMG New Data Sheet RBI Add power up requirements to maximum ratings information CY28343 Description of Change Page ...