CY28344 Cypress Semiconductor, CY28344 Datasheet

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CY28344

Manufacturer Part Number
CY28344
Description
FTG
Manufacturer
Cypress Semiconductor
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07113, Rev. *A
Features
• C
• System frequency synthesizer for Intel Brookdale (845)
• Programmable clock output frequency with less than
• Integrated fail-safe Watchdog timer for system
• Automatically switch to HW-selected or
Block Diagram
VTTPWRGD/PD#
Synthesizer/Driver Specifications
and Brookdale G Pentium® 4 Chipsets
1MHz increment
recovery
SW-programmed clock frequency when Watchdog
timer time-out
MULTSEL0
ompatible to Intel® CK-Titan and CK-408 Clock
SDATA
FS0:4
SCLK
X1
X2
PLL 1
PLL2
SMBus
Logic
XTAL
OSC
Network
Divider
PLL Ref Freq
2
FTG for Intel Pentium 4 CPU and Chipsets
3901 North First Street
VDD_3V66
VDD_3V66
48MHz
VDD_REF
REF_2X
VDD_CPU
CPU0:2, CPU0:2#,
3V66_1:3
3V66_0/VCH_CLK
VDD_PCI
VDD_48MHz
24_48MHz
RST#
PCI0:6
PCI_F0:1
PRELIMINARY
• Capable of generating system RESET after a Watchdog
• Support SMBus byte Read/Write and block Read/Write
• Vendor ID and Revision ID support
• Programmable drive strength support
• Programmable output skew support
• Power management control inputs
• Available in 48-pin SSOP
Note:
1.
timer time-out occurs or a change in output frequency
via SMBus interface
operations to simplify system BIOS development
^FS0/PCI_F0
^FS1/PCI_F1
CPU
VDD_CORE
×3
Pin Configuration
GND_3V66
VDD_3V66
GND_REF
VDD_REF
GND_PCI
GND_PCI
VDD_PCI
VDD_PCI
Signals marked with “*” and “^,” respectively, have internal pull-up and
pull-down resistors.
3V66_1
3V66_2
3V66_3
RST#
PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
San Jose
X1
X2
3V66
×4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP-48
[1]
CA 95134
PCI
×9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Revised December 26, 2002
REF_2X/FS2^
CPU0
CPU0#
VDD_CPU
CPU1
CPU1#
GND_CPU
VDD_CPU
CPU2
CPU2#
MULTSEL0
IREF
GND_CPU
48MHz/FS3^
24_48MHz
VDD_48MHz
GND_48MHz
3V66_0/VCH_CLK/FS4^
VDD_3V66
GND_3V66
SCLK
SDATA
VTTPWRGD/PD#*
GND_CORE
REF
×1
CY28344
408-943-2600
48M
×2

Related parts for CY28344

CY28344 Summary of contents

Page 1

... VDD_48MHz 3V66_3 48MHz RST# VDD_CORE 24_48MHz 2 RST# Note: 1. Signals marked with “*” and “^,” respectively, have internal pull-up and pull-down resistors. • 3901 North First Street • CY28344 3V66 PCI REF ×4 ×9 ×1 [ REF_2X/FS2 CPU0 X2 ...

Page 2

... Power Connection: Power supply for CPU outputs buffers, 3V66 output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. P 3.3V Power Connection: 48MHz output buffers. Connect to 3.3V. G Ground Connection: Connect all ground pins to the common system ground plane. CY28344 Pin Description Page ...

Page 3

... IREF = 2. Ohm Rr = 475 1%, IREF = 2. Ohm Rr = 475 1%, IREF = 2. Ohm Rr = 475 1%, IREF = 2.32 mA Reference R, IREF = VDD/(3*Rr 221 1%, IREF = 5. 221 1%, IREF = 5. 221 1%, IREF = 5. 221 1%, IREF = 5.00 mA CY28344 Pin Description Output Current 4*Iref 1. 4*Iref 1. 5*Iref 1.25V @ 5*Iref 1. ...

Page 4

... Acknowledge from slave 30:37 Byte count from slave – 8 bits 38 Acknowledge 39:46 Data byte from slave – 8 bits 47 Acknowledge 48:55 Data byte from slave – 8 bits 56 Acknowledge ... Data bytes from slave/acknowledge ... Data byte N from slave – 8 bits ... Not acknowledge ... Stop CY28344 Description Page ...

Page 5

... SW Frequency selection bits. See Table Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings SW Frequency selection bits. See Table OFF Enabled Reserved Description (Active/Inactive) (Active/Inactive) (Active/Inactive) Latched FS[4:0] inputs. These bits are Read-only. CY28344 Description Power On Default ...

Page 6

... SW control; IREF multiplier is determined by Byte[4], Bit[5:6]. IREF multiplier 00 = Ioh is 4 × IREF 01 = Ioh is 5 × IREF 10 = Ioh is 6 × IREF 11 = Ioh is 7 × IREF (Active/Inactive) Drive 0 = Normal HIGH (Active/Inactive) (Active/Inactive) (Active/Inactive) CY28344 Power On Default Power On Default ...

Page 7

... Bit[2] of Cypress Vendor ID. This bit is Read-only. Bit[1] of Cypress Vendor ID. This bit is Read-only. Bit[0] of Cypress Vendor ID. This bit is Read-only. Pin Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Reserved Reserved CY28344 Power On Default Power On Default 0 0 ...

Page 8

... Watchdog timer time-out occurs. Under recovery frequency mode, CY28344 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock CY28344 from its recovery frequency mode by clearing the WD_EN bit ...

Page 9

... Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL From latched FS[4: From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] CY28344 Power On Default ...

Page 10

... When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Pin Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved. Write with “1” Reserved. Write with “1” CY28344 Power On Default Power On Default ...

Page 11

... Bit 0 -- Reserved Document #: 38-07113, Rev. *A PRELIMINARY Pin Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CY28344 Power On Default Power On Default Page ...

Page 12

... CY28344 PLL Gear Constants 3V66 PCI (G) 67.27 33.63 48.00741 66.67 33.33 48.00741 68.67 34.33 48.00741 70.00 35.00 48.00741 71.33 35.67 48.00741 72.67 36.33 48.00741 74.00 37.00 48.00741 76.00 38.00 48.00741 78.00 39.00 48.00741 80.00 40.00 48.00741 84.67 42.33 48.00741 86 ...

Page 13

... Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in the following table. Description CY28344 Page ...

Page 14

... M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Fixed Value for M-Value Register 93 45 CY28344 Range of N-Value Register for Different CPU Frequency 97 – 255 127 – 245 Page ...

Page 15

... PCI 48 MHz, REF, 3V66 PCI 0 < V < < V < For I = 6*IRef Configuration OH REF, 48 MHz 3V66, PCI REF, 48 MHz 3V66, PCI, Three-state CPU VDD_CORE/VDD3.3 = 3.465V CY28344 Min. Max. 3.135 3.465 2.85 3.465 22 14.318 14.318 Min. Max. Unit /2 2 – ...

Page 16

... Measured single ended waveform from 0.175V to 0.525V Measured at Crossover Measured at Crossover t With all outputs running Measured with test loads Measured with test loads Measured with test loads Measured with test loads = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V. DD CY28344 Min. Max 0.5 2.0 1.0 4.0 500 175 500 1 ...

Page 17

... Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock Skew 3V66 3V66 t 5 Document #: 38-07113, Rev. *A PRELIMINARY CY28344 Page ...

Page 18

... Switching Waveforms (continued) PCI-PCI Clock Skew PCI PCI t 6 3V66-PCI Clock Skew 3V66 PCI t 7 CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK Document #: 38-07113, Rev. *A PRELIMINARY CY28344 Page ...

Page 19

... *Option Core pin = 0.1 uF Low ESR DD CY28344 VDDQ3 34 *Option Page ...

Page 20

... Ref,USB Outputs 20 pF PCI,3V66 Outputs = 33 ohm ohm 14, 19, 25, 29, 32, 36 13, 18, 24, 30, 33, 41, 45 Ref,USB Outputs 20 pF PCI,3V66 Outputs 1.0V Amplitude Package Type CY28344 0.7V Test Load 2pF CPU OUTPUTS 2pF 1.0V Test Load ...

Page 21

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 48-lead Shrunk Small Outline Package O48 CY28344 51-85061-B Page ...

Page 22

... Document Title: CY28344 FTG for Intel Pentium 4 CPU and Chipsets Document Number: 38-07113 Issue REV. ECN NO. Date ** 110805 12/11/01 *A 122788 12/26/02 Document #: 38-07113, Rev. *A PRELIMINARY Orig. of Change Description of Change IKA Adding switching characteristics. Added notes to operating conditions. RBI Add power up requirements to maximum ratings information. ...

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