CY28401 Cypress Semiconductor, CY28401 Datasheet
CY28401
Manufacturer Part Number
CY28401
Description
100-MHz Differential Buffer for PCI Express and SATA
Manufacturer
Cypress Semiconductor
Datasheet
1.CY28401.pdf
(14 pages)
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Cypress Semiconductor Corporation
Document #: 38-07592 Rev. **
Features
• CK409 or CK410 companion buffer
• Eight differential 0.7v clock pairs
• Individual OE controls
• Low CTC jitter (< 50 ps)
• Programmable bandwidth
• SRC_STOP# power management control
• SMBus Block/Byte/Word Read and Write support
• 3.3V operation
• PLL Bypass-configurable
• Divide by 2 programmable
• 48-pin SSOP package
Block Diagram
PLL/BYPASS#
SRC_STOP#
SRC_DIV2#
PWRDWN#
HIGH_BW#
SRCC_IN
SRCT_IN
OE_[0:7]
SDATA
SCLK
100-MHz Differential Buffer for PCI Express and SATA
PLL
Controller
Control
SMBus
Output
DIV
•
Output
Buffer
3901 North First Street
DIFT0
DIFC0
DIFT1
DIFC1
DIFT2
DIFC2
DIFT3
DIFC3
DIFT4
DIFC4
DIFT5
DIFC5
DIFT6
DIFC6
DIFT7
DIFC7
LOCK
Functional Description
The CY28401 is a differential buffer and serves as a
companion device to the CK409 or CK410 clock generator.
The device is capable of distributing the Serial Reference
Clock (SRC) in PCI Express and SATA implementations.
PLL/BYPASS#
SRC_DIV2#
•
SRCC_IN
SRCT_IN
SDATA
DIFCO
DIFC1
DIFC2
DIFC3
DIFT0
DIFT1
DIFT2
DIFT3
SCLK
OE_0
OE_3
OE_1
OE_2
San Jose
VDD
VDD
VDD
VSS
VSS
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
,
Pin Configuration
CA 95134
48 SSOP
Revised November 24, 2003
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
•
408-943-2600
CY28401
VDD_A
VSS_A
IREF
LOCK
OE_7
OE_4
DIFT7
DIFC7
VSS
VDD
DIFT6
DIFC6
OE_6
OE_5
DIFT5
DIFC5
VSS
VDD
DIFT4
DIFC4
HIGH_BW#
SRC_STOP#
PWRDWN#
VSS
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