CY28442 Cypress Semiconductor, CY28442 Datasheet
CY28442
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CY28442 Summary of contents
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... CPUC_ITP/SRCC7 VDD_SRC SRCT[1:5] CPUC[1:5] VDD_PCI PCI VDD_PCI PCIF VDD_48MHz 96_100_SSCT Divider 96_100_SSCC VDD_48MHz DOT96T Divider DOT96C VDD_48 USB • 3901 North First Street CY28442 Alviso Chipset SRC PCI REF DOT96 x5 PCI2/SEL_CLKREQ VDD_REF 2 55 VSS_REF PCI_STP# PCI3 ...
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... PWR 3.3V power supply for PLL. GND Ground for PLL precision resistor is attached to this pin, which is connected to the internal current reference. PWR 3.3V power supply for outputs. O, DIF Differential CPU clock outputs. GND Ground for outputs. I SMBus-compatible SCLOCK. I/O SMBus-compatible SDATA. CY28442 Description Page ...
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... Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description CY28442 Description ,V specifications. IL_FS IH_FS ...
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... Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop CY28442 Block Read Protocol Description Byte Read Protocol Description Page ...
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... PCI5 Output Enable 0 = Disabled Enabled PCI4 PCI4 Output Enable 0 = Disabled Enabled PCI3 PCI3 Output Enable 0 = Disabled Enabled PCI2 PCI2 Output Enable 0 = Disabled Enabled Reserved, Set = 1 Reserved, Set = 1 Reserved, Set = 1 PCIF1 PCIF1 Output Enable 0 = Disabled Enabled CY28442 Description Description Description Page ...
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... Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CY28442 Description Description Description Page ...
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... SRC[T/C]5 CLKREQ#B control 1 = SRC[T/C]5 stoppable by CLKREQ#B pin 0 = SRC[T/C]5 not controlled by CLKREQ#B pin SRC[T/C]3 CLKREQ#B control 1 = SRC[T/C]3 stoppable by CLKREQ#B pin 0 = SRC[T/C]3 not controlled by CLKREQ#B pin SRC[T/C]1 CLKREQ#B control 1 = SRC[T/C]1 stoppable by CLKREQ#B pin 0 = SRC[T/C]1 not controlled by CLKREQ#B pin CY28442 Description Description Description Description Page ...
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... SRC[T/C]4 CLKREQ#B control 1 = SRC[T/C]4 stoppable by CLKREQ#B pin 0 = SRC[T/C]4not controlled by CLKREQ#B pin SRC[T/C]2 CLKREQ#B control 1 = SRC[T/C]2 stoppable by CLKREQ#B pin 0 = SRC[T/C]2 not controlled by CLKREQ#B pin RESERVED SRC[T/C]7CLKREQ#A control 1 = SRC[T/C]7 stoppable by CLKREQ#A pin 0 = SRC[T/C]7 not controlled by CLKREQ#A pin CY28442 Description Description Description Page ...
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... CLKREQ#A The CY28442 requires a Parallel Resonance Crystal. Substi- tuting a series resonance crystal will cause the CY28442 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading ...
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... CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance 1 (lead frame, bond wires etc.) ) Ce2 + Cs2 + Ci2 CY28442 Pin Cs2 Trace 2.8pF Trim 33pF Page ...
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... CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100,133,166,200,266,333 and 400MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 uS after asserting Vtt_PwrGd#. CY28442 Page ...
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... CPUC clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal (Iref), and the CPUC signal will be Tri-stated. CY28442 Page ...
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... CPUC CPUT Internal CPUC Internal CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven Document #: 38-07680 Rev. ** ADVANCE INFORMATION Figure 6. CPU_STP# Assertion Waveform Tdrive_CPU_STP#,10nS>200mV Figure 7. CPU_STP# Deassertion Waveform CY28442 1.8mS Page ...
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... PCI_STP# going LOW Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. Tsu Figure 10. PCI_STP# Assertion Waveform Tdrive_SRC Tsu Figure 11. PCI_STP# Deassertion Waveform CY28442 1.8mS ). (See SU Page ...
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... Sample Sels Delay VTT_PW RGD# State 1 State 2 On Figure 12. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28442 Device is not affected, VTT_PW RGD# is ignored State Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
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... SDATA, SCLK except internal pull-up resistors, 0 < V except internal pull-down resistors, 0 < – max. load and freq. per Figure 15 PD asserted, Outputs Driven PD asserted, Outputs Tri-state Current in tri-state mode CY28442 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD – ...
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... Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured from V = 0.175 0.525V Determined as a fraction of 2*(T T )/( Math averages Figure 15 Math averages Figure 15 CY28442 Min. Max. 47.5 52.5 69.841 71.0 and 0.7V – 10 – 500 – 300 ...
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... Math averages Figure 15 Math averages Figure 15 See Figure 15. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V CY28442 Min. Max. V HIGH – 0.3 –0.3 – 0 9.997001 10.00300 OX 9 ...
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... Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Output under Test tDC 3. Figure 14. Single ended PCI lumped load configuration CY28442 Min. Max. = 0.175 175 700 – R – – 125 – 125 660 850 – ...
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... Package Type CY28442 Product Flow Commercial, 0° to 85°C Commercial, 0° to 85°C ...
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... SEATING 0.279[0.011] PLANE 2 C system, provided that the system conforms to the I CY28442 DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. GAUGE PLANE 0.25[0.010] 0.508[0.020] 0.762[0.030] 0° ...
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... Document History Page Document Title: CY28442 Clock Generator for Intel Document Number: 38-07680 REV. ECN NO. Issue Date ** 237648 See ECN Document #: 38-07680 Rev. ** ADVANCE INFORMATION Alviso Chipset Orig. of Change RGL New Data Sheet CY28442 Description of Change Page ...