IDT72V221L15J IDT, Integrated Device Technology Inc, IDT72V221L15J Datasheet - Page 9
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IDT72V221L15J
Manufacturer Part Number
IDT72V221L15J
Description
IC FIFO SYNC 1KX9 15NS 32PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V221L15PFG.pdf
(14 pages)
Specifications of IDT72V221L15J
Function
Synchronous
Memory Size
9K (1K x 9)
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Configuration
Dual
Density
9Kb
Access Time (max)
10ns
Word Size
9b
Organization
1Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
PLCC
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
20mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Lead Free Status / Rohs Status
Not Compliant
Other names
72V221L15J
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V221L15J
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V221L15J8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V221L15JI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V221L15JI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. t
NOTE:
1. When t
Q
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
(If Applicable)
WCLK
WEN2
REN2
WEN1
RCLK
REN1,
0
the rising edge of RCLK and the rising edge of WCLK is less than t
When
The Latency Timings apply only at the Empty Boundary (EF = LOW).
- Q
SKEW1
OE
EF
8
Q
D
t
WCLK
WEN2
0
SKEW1
SKEW1
WEN1
REN2
is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between
RCLK
0
REN1,
- Q
- D
OE
EF
≥ minimum specification, t
< minimum specification, t
8
8
t
ENS
t
OLZ
t
FRL
ENS
t
t
FRL
ENS
ENH
= 2t
= t
CLK
CLK
t
t
DS
t
SKEW1
CLKH
+ t
+ t
t
REF
t
SKEW1
SKEW1
A
t
OE
or t
Figure 7. First Data Word Latency Timing
CLK
t
NO OPERATION
CLK
+ t
Figure 6. Read Cycle Timing
SKEW1
D
SKEW1
0
(First Valid Write)
, then EF may not change state until the next RCLK edge.
t
t
CLKL
OLZ
t
t
REF
FRL
VALID DATA
(1)
9
t
OHZ
t
ENS
D
1
t
OE
t
SKEW1
(1)
t
A
t
REF
D
2
COMMERCIAL AND INDUSTRIAL
D
0
t
A
TEMPERATURE RANGES
OCTOBER 22, 2008
D
3
D
4092 drw09
4092 drw08
1