CY28RS480-1 Cypress Semiconductor, CY28RS480-1 Datasheet
CY28RS480-1
Related parts for CY28RS480-1
CY28RS480-1 Summary of contents
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... VDD_48 MHz VSS_SRC SRCT4 SRCC4 SRCT3 USB_48 SRCC3 VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC SRCST1 SRCSC1 • 3901 North First Street • San Jose CY28RS480-1 RS480 Chipset HTT66 PCI REF USB_48 VDD_REF 2 55 VSS_REF 3 54 REF0 ...
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... O 14.318-MHz Crystal Output I,PU 3.3V LVTTL Input When this pin is asserted HIGH, all clock outputs except for CPUCLKs (pins 41, 40, 45, 44) are halted at logic level 0. This pin has internal pull-up No Connects CY28RS480-1 Description K8 buffer (200 MHz). Type-5 buffer. Page Datasheet pdf - http://www.DataSheet4U.net/ ...
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... Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge Byte Read Protocol Bit 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave CY28RS480-1 Description Description Page Datasheet pdf - http://www.DataSheet4U.net/ ...
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... Disable Enable REF1 Output Enable 0 = Disable Enable REF0 Output Enable 0 = Disable Enable PCI0 Output Enable 0 = Disable Enable USB_48MHz Output Enable 0 = Disable Enable RESERVED CPU[T/C]1 Output Enable 0 = Disable (Hi-Z Enable CPU[T/C]0 Output Enable 0 = Disable (Hi-Z Enable CY28RS480-1 Description Page Datasheet pdf - http://www.DataSheet4U.net/ ...
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... SRC[T/C]2 CLKREQ#0 control 1 = SRC[T/C]2 stoppable by CLKREQ#0 pin 0 = SRC[T/C]2 free running SRC[T/C]1 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running SRC[T/C]0 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running HTT66 Output enable 0 = disabled enabled Reserved CY28RS480-1 Page Datasheet pdf - http://www.DataSheet4U.net/ ...
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... REF Output drive strength 0 = Low drive high drive Reserved Reserved Reserved Reserved Reserved Description Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 CY28RS480-1 Page Datasheet pdf - http://www.DataSheet4U.net/ ...
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... Crystal Recommendations The CY28RS480-1 requires a parallel resonance crystal. Substituting a series resonance crystal will cause the CY28RS480-1 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... SRC outputs resuming simultaneously. If the CLKREQ# drive mode bit is programmed to ‘1’ three-state), the all stopped SRC outputs must be driven high within CLKREQ#[1:0] deassertion to a voltage greater than 200 mV. www.DataSheet.co.kr CY28RS480-1 Page Datasheet pdf - http://www.DataSheet4U.net/ ...
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... Figure 4. CLK_STOP Assertion Timing Waveform CPU_CLOCK CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz PCI, 33MHz REF Figure 5. CLK_STOP Deassertion Timing Waveform Document #: 38-07714 Rev. *C PRELIMINARY Tstable < 2 REFCLK www.DataSheet.co.kr Tdrive_PWRDN# <300µS, >200mV CY28RS480-1 Page Datasheet pdf - http://www.DataSheet4U.net/ ...
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... The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3V and 0. average over 1-µs duration Over 150 ms CY28RS480-1 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V – ...
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... Measured from V = 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 8 Math averages Figure 8 See Figure 8. Measure SE Measured at 1.5V Measured at 20% and 60% Measured at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V CY28RS480-1 Min. Max. Unit 1.6 7 V/ns 0.4 2.3 V – 250 ps –150 150 mV 1.05 1.45 V 0.97 1.45 V –200 200 mV ...
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... Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V@1 µs Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V for www.DataSheet.co.kr High drive strength Measurement at 1.5V CY28RS480-1 Min. Max. Unit 29.9910 30.15980 ns 29.49100 30.50900 ns 29.49100 30.65980 ns 12.0 – nS 12.0 – nS ...
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... Figure 6. Single-ended Load Configuration www.DataSheet.co. CY28RS480-1 Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF - Page Datasheet pdf - http://www.DataSheet4U.net/ ...
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... F Figure 8. 0.7V Load Configuration 125 ohms 3900pF 169 ohms 3900pF www.DataSheet.co.kr Figure 9. CPU Output Load Configuration Package Type CY28RS480 Vbias=1.25V 125 ohms 5pF 5pF Product Flow Commercial, 0 ° ° C Commercial, 0 ° ° C Commercial, 0 ° ...
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... GAUGE PLANE MAX. 0.25[0.010] 0.20[0.008] 0.051[0.002] 0.152[0.006] 0.170[0.006] SEATING 0.279[0.011] PLANE 2 C system, provided that the system conforms to the I CY28RS480-1 DIMENSIONS IN INCHES MIN. MAX. 0.005 0.010 0.024 0.040 0°-8° 51-85062-*C DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0 ...
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... Document History Page Document Title: CY28RS480-1 Clock Generator for ATI Document Number: 38-07714 REV. ECN NO. Issue Date ** 204582 See ECN *A 304231 See ECN *B 339334 See ECN *C 390576 See ECN Document #: 38-07714 Rev. *C PRELIMINARY RS480 Chipset Orig. of Change Description of Change RGL ...