CY29973 Cypress Semiconductor, CY29973 Datasheet - Page 6

• Manufacturer Part Number: CY29973
• Description: 3.3V 125-MHz Multi-Output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor

Power Management
The individual output enable or freeze control of the CY29973 allows the user to implement unique power management schemes into
the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains
one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs can not be frozen with the serial
port, this avoids any potential lock up situation must an error occur in the loading of the serial data. An output is frozen when a logic
‘0’ is programmed and enabled when a logic ‘1’ is written. The enabling and freezing of individual outputs is done in such a manner
as to eliminate the possibility of partial “runt” clocks.
The serial input register is programmed through the SDATA input by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable bits.
The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK.
Absolute Maximum Conditions
Maximum Input Voltage Relative to V
Maximum Input Voltage Relative to V
Storage Temperature: ................................ - 65°C to + 150°C
Operating Temperature:................................ - 40°C to +85°C
Maximum ESD protection............................................... 2 kV
Maximum Power Supply:................................................ 5.5V
Maximum Input Current:................................................ ± 20 mA
DC Electrical Specifications
Document #: 38-07291 Rev. *C
V
V
V
V
I
I
V
V
I
I
Notes
IL
IH
DDQ
DDA
3. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
4. The V
5. Inputs have pull up/pull down resistors that effect input current.
6. Driving series or parallel terminated 50Ω (or 50Ω to V
Parameter
IL
IH
PP
CMR
OL
OH
and the input lies within the V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the V
Input Low Voltage
Input High Voltage
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range PECL_CLK
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Quiescent Supply Current
PLL Supply Current
PP
Description
specification.
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
[5]
[5]
Start
[6]
[6]
Bit
SS
DD
:.............. V
:............. V
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
V
DD
[3]
= 2.9V to 3.6V, V
DD
/2) transmission lines.
[4]
DD
SS
Figure 2. Control Bit Map
+ 0.3V
- 0.3V
I
I
V
OL
OH
DD
= 20 mA
= –20 mA
only
DDC
Conditions
= 3.3V ±10%, T
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions must be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, V
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
< (V
in
or V
in
and V
A
out
= - 40°C to +85°C
) < V
out
SS
DD
must be constrained to the range:
or V
V
DD
Min
V
300
2.0
2.4
DD
–
–
–
–
–
SS
– 2.0
).
Typ.
10
15
–
–
–
–
–
–
–
–
V
DD
1000
–120
Max
V
120
0.8
0.5
15
20
CY29973
DD
–
– 0.6
Page 6 of 9
CMR
range
Unit
mV
mA
mA
μA
μA
V
V
V
V
V
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