CY2DL1510 Cypress Semiconductor, CY2DL1510 Datasheet - Page 13

• Manufacturer Part Number: CY2DL1510
• Description: 1:10 Differential LVDS Fanout Buffer
• Manufacturer: Cypress Semiconductor

Document History Page
Document Number: 001-54863 Rev. *H
Revision
Document Title: CY2DL1510 1:10 Differential LVDS Fanout Buffer
Document Number: 001-54863
*C
*D
*A
*B
*E
**
2744225
2782891
2838916
2885033
3011766
3017258
ECN
Orig. of Change
CXQ/PYRS
CXQ
CXQ
CXQ
CXQ
CXQ
Submission
01/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”.
02/26/2010 Updated 32-Pin TQFP package diagram.
08/20/2010 Changed maximum additive jitter from 0.25 ps to 0.11 ps in “Features”
08/27/2010 Corrected Output Rise/Fall time diagram.
08/19/09
10/09/09
Date
New datasheet.
Updated format of Logic Block Diagram on page 1.
Added T
Added T
Changed equation for RMS jitter in Figure 8 to proportionality.
Changed package drawing from 1.4 mm thickness 51-85088 spec to
1.0 mm thickness 51-850063 spec.
Added “Synchronous Clock Enable Function” to Features on page 1.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features”
on page 1 and in t
Added t
Removed V
page 4.
Added V
V
Added internal pullup resistance spec for CLK_EN in the DC Electrical
Specs table on page 4. Min = 60 k Ω , Max = 140 k Ω .
Added a measurement definition for C
on page 4.
Changed letter case and some names of all the timing parameters in the
AC Electrical Specs table on page 5 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 5.
Added condition to t
page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in
Figures 5, 6, 7, and 9, to be consistent with EROS. Updated Figure 4
with definitions for V
on page 1 and in t
Changed max t
Added note 5 to describe I
Removed reference to data distribution from “Functional Description”.
Changed R
Block Diagram and from 60 k Ω min / 140 k Ω max to 90 k Ω min / 210 k Ω
max in the DC Electrical Specs table.
Added V
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset
to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC
Electrical Specs table.
Added “Frequency range up to 1 GHz” condition to t
Added Acronyms and Ordering Code Definition.
PP
min = 250 mV and max = 470 mV; Δ V
PU
SOD
SETUP
PP
ID
spec to the Operating Conditions table on page 3.
max spec of 0.8V in the DC Electrical Specs table.
and Δ V
P
OD
and T
for differential inputs from 100 k Ω to 150 k Ω in the Logic
and T
and Δ V
PD
JIT
JIT
spec from 480 ps to 600 ps.
PP
SOE
R
PP
HOLD
in the AC Electrical Specs table on page 5.
in the AC Electrical Specs table on page 5.
specs to the AC Electrical Specs table on page 5.
and t
OD
specs (700 ps max) to AC Specs table.
and Δ V
Description of Change
specs from the DC Electrical Specs table on
IH
specs (300 ps min) to AC Specs table.
F
specs in the AC Electrical specs table on
and I
PP
.
IL
specs.
IN
in the DC Electrical Specs table
PP
max = 50 mV.
CY2DL1510
ODC
spec.
Page 13 of 15
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