CY2DL814 Cypress Semiconductor, CY2DL814 Datasheet

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CY2DL814

Manufacturer Part Number
CY2DL814
Description
1:4 Clock Fanout Buffer
Manufacturer
Cypress Semiconductor
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07057 Rev. *A
Features
• Low-voltage operation
• V
• 1:4 Fanout
• Single-input configurable for
• Drives 50- or 100-ohm load (selectable)
• Low input capacitance
• Low output skew
• Does not exceed Bellcore 802.3 standards
• Operation at
• Low propagation delay Typical (tpd < 4 ns)
• Industrial versions available
• Packages available include TSSOP/SOIC
Block Diagram
— LVDS, LVPECL, or LVTTL
— Four differential pairs of LVDS outputs
DD
CONFIG
IN+
IN-
= 3.3V
EN1
EN2
LVPECL /
LVDS /
CNTRL
LVTTL
350 MHz – 700 Mbps
3901 North First Street
OUTPUT
LVDS
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Description
The Cypress CY2 series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DL814 fanout buffer features a single
LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS
output pairs.
Designed for data-communication clock management applica-
tions, the fanout from a single input reduces loading on the
input clock.
The CY2DL814 is ideal for both level translations from single
ended to LVDS and/or for the distribution of LVDS-based clock
signals. The Cypress CY2DL814 has configurable input and
output
LVPECL/LVTTL or LVDS signals while the output driver’s
support standard and high drive LVDS. Drive either a 50-ohm
or 100-ohm line with a single part number/device.
functions.
San Jose
1:4 Clock Fanout Buffer
Pin Configuration
CONFIG
CNTRL
GND
VDD
EN2
EN1
IN+
IN-
The
16-pin TSSOP/SOIC
1
2
3
4
5
6
7
8
input
CA 95134
ComLink™ Series
Revised December 14, 2002
can
16
15
14
13
12
11
10
9
be
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
CY2DL814
selectable
408-943-2600
for

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CY2DL814 Summary of contents

Page 1

... Designed for data-communication clock management applica- tions, the fanout from a single input reduces loading on the input clock. The CY2DL814 is ideal for both level translations from single ended to LVDS and/or for the distribution of LVDS-based clock signals. The Cypress CY2DL814 has configurable input and output functions ...

Page 2

... IN+ IN– Drive STD Impedance Standard 100 ohm High Drive/Bus/B 100 ohm ComLink™ Series CY2DL814 Description + – /IN ), (EN, EN#) from the default Outputs QnA Output Voltage Value V0 = Voutput 50 ohm ohm ...

Page 3

... Conditions Guaranteed Logic High Level V = Max Max Max (Max ComLink™ Series CY2DL814 Input Receiver Type Output Logic Q Pins, Q1A or Q1 True Invert True Invert Min. Typ. Max. 1.5 2.0 90 100 Min. Typ. 100 IVIDI/2 2.4–(IVIDI/2) Config/Cntrl Pins ...

Page 4

... RL and and C intrinsic CL– and and C intrinsic = 3.3V ±5%, Temperature = –40°C to +85°C) DD Description V ) PLH V ComLink™ Series CY2DL814 Min. Typ 2. 0.5V IN –0.7 80 Min. Typ. Max 100 ohm 0.25 – 100 ohm 925 Min ...

Page 5

... (Min.)/V (Max.)(Limit) OUT OH OL Standard Termination 1 PLH T PHL V0Y - V0Z Standard Termination V I(A) 2.0V V I(B) 1.6V ComLink™ Series CY2DL814 Min. Typ. 1 TPA 50 10pF TPC 50 TPB 1 Differential 1 Differential 1.0 V 80% 0V Differential 20% [3,4,5,6] TPA 50 TPC 50 TPB VOC VOD Next Device ...

Page 6

... Part Number CY2DL814ZI CY2DL814ZIT CY2DL814SI CY2DL814SIT CY2DL814ZC CY2DL814ZCT CY2DL814SC CY2DL814SCT Notes: 7. LVCMOS/LVTTL single ended input value. Ground either input: when on the B side then non-inversion takes place side is grounded, the signal becomes the complement of the input on B side. See Table 4. 8. ...

Page 7

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 16-lead (150-mil) Molded SOIC S16 ComLink™ Series CY2DL814 51-85068-A 51-85091 Page ...

Page 8

... Document Title: ComLink™ Series CY2DL814 1:4 Clock Fanout Buffer Document Number: 38-07057 Issue REV. ECN NO. Date ** 115362 07/10/02 *A 122744 12/14/02 Document #: 38-07057 Rev. *A Orig. of Change Description of Change EHX New Data Sheet RBI Added power up requirements to maximum ratings information. ComLink™ Series CY2DL814 Page ...

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