AN2316 Freescale Semiconductor / Motorola, AN2316 Datasheet - Page 5

• Manufacturer Part Number: AN2316
• Description: Connecting an MSC8102 TDM to a Time-Slot Interchange Switching Device
• Manufacturer: Freescale Semiconductor / Motorola

1.3 Channel Parameter Registers
1.4 Control Registers
The channel parameter registers determine the parameters of each channel, such as the buffer location,
channel type, and channel activation. Channels that are not used should be clear. In this example the
receive and transmit TDM buffers reside in M2 memory in consecutive order and all the channels are
active and transparent. Table 4 describe the receive and transmit channel parameter registers.
The control registers set the threshold pointers and enable TDM events. The threshold registers determine
the offset in the data buffers that cause interrupts to be generated. Here, the receive first threshold
interrupt is generated when the first half of the buffer is filled with new data, and the second receive
threshold interrupt is generated when the second half of the buffer is full. The transmit first threshold
interrupt is generated when the TDM reads the first half of the buffer, and the second threshold interrupt
is generated when the TDM reads the second half of the buffer. The TDM0RIER and TDM0TIER
registers enable interrupt generation, and a value of zero written into the appropriate field disables
interrupt generation.
TDM0RCPR0 = 0x80000000
TDM0RCPR1 = 0x80000040
TDM0RCPR2 = 0x80000080
:
TDM0RCPR63 = 0x80000FC0
TDM0TCPR0 = 0x80001000
TDM0TCPR1 = 0x80001040
TDM0TCPR2 = 0x80001080
TDM0TCPR31 = 0x80001FC0
Note: All the receive and transmit channels are active and transparent.
TDM0TDBFT[8–31]:TDBFT = 0x000018
Register Setting
Freescale Semiconductor, Inc.
Bits fields Setting
For More Information On This Product,
Table 4. Receive/transmit Channel Parameter Registers
Go to: www.freescale.com
Table 5. Receive and Transmit Threshold Registers
The receive data buffer of channel 0 is located at an offset of 0 (refer to the TDMx
Receive Global Base Address Register, TDMxRGBA[16–31]:RGBA field). The
data buffer address is 0x200000 (local memory address space).
The receive data buffer of channel 1 is located at an offset of 64 bytes (refer to the
TDMxRGBA[16–31]:RGBA field). The data buffer address is 0x200040 (local
memory address space).
The receive data buffer of channel 2 is located at an offset of 128 bytes (refer to
the TDMxRGBA[16–31]:RGBA field). The data buffer address is 0x200080 (local
memory address space).
The receive data buffer of channel 63 is located at address 0x200FC0 (local
memory address space).
The transmit data buffer of channel 0 is located at an offset of 4096 bytes (refer to
the TDMx Transmit Global Base Address Register, TDMxTGBA[16–31]:TGBA
field). The address of transmit channel 0 is 0x201000 (local memory address
space).
The transmit data buffer of channel 1 is located at an offset of 4160 bytes (refer to
the TDMxTGBA[16–31]:TGBA field). The address of transmit channel 1 is
0x201040 (local memory address space).
The transmit data buffer of channel 3 is located at address 0x201080 (local
memory address space).
The transmit data buffer of channel 63 is located at address 0x201FC0 (local
memory address space).
The transmit first threshold interrupt is generated when the first half of
the data buffer is empty.
Description
Description
Configuring the MSC8102 TDM
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