AN2321 Freescale Semiconductor / Motorola, AN2321 Datasheet - Page 20

• Manufacturer Part Number: AN2321
• Description: Designing for Board Level Electromagnetic Compatibility
• Manufacturer: Freescale Semiconductor / Motorola

AN2321/D
PART 3:
PRINTED CIRCUIT BOARD LAYOUT TECHNIQUES
PCB Basic
Characteristics
20
In addition to component selection and circuit design, good printed circuit board
(PCB) layout is an important factor in EMC performance. Since the PCB is an
inherent part of the system, EMC enhancements by PCB layout does not add
extra cost towards the finish product.
One point to note is that there are no fast and strict rules for PCB layout. There
is no single rule that covers all PCB layouts. Most PCB layouts are restricted
by board size and the number of copper layers. Some layout techniques may
apply to one type of circuit but not another. Much of it will depend on the
experience of the PCB layout engineer.
Nevertheless, there are some general rules. These are discussed in the
following sections. These should be treated as general guidelines. One must
remember that poor PCB layouts can cause more EMC problems than it can
cure, and in many cases, adding filters and components cannot solve the
problem. In the end, it may be better to do a complete re-layout of the board.
Therefore, good PCB layout practice at the outset is the best cost saving
method.
A PCB is constructed using a series of laminates, tracking and prepreg layers
in a vertical stack. In multi-layer PCBs, most designers will place the signalling
tracking on either outer layer for easier debugging of the board.
A track on the PCB has resistance, capacitance, and inductance.
For a 1oz. copper track, 0.5mm (20mil) width, 20mm (800mil) long over
ground plane on a 0.25mm (10mil) thick FR4 laminate would exhibit a
resistance of 9.8m Ω , an inductance of 20nH and a capacitance coupling to
ground of 1.66pF.
Designing for Board Level Electromagnetic Compatibility
Freescale Semiconductor, Inc.
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Resistance: the resistance of the track is determined by the weight of
copper and cross-sectional area. For example, there are 0.49m Ω /unit
area in 1oz. copper weight.
Capacitance: the capacitance of the track is determined by the dielectric
( EoEr ), coverage area ( A ), and distance between track ( h ).
The equation is C = EoErA/h , where Eo is the dielectric constant of free
space (8.854pF/m) and Er is the relative dielectric constant of the PCB
substrate (4.7 for FR4 laminate).
Inductance: the inductance of the track is evenly distributed in the track
at approximately 1nH/m.
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