CY2XP304 Cypress Semiconductor, CY2XP304 Datasheet
CY2XP304
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CY2XP304 Summary of contents
Page 1
... CLK3B • San Jose CA 95134 • Revised July 28, 2004 CY2XP304 408-943-2600 ...
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... Figure 2 shows the serial interface transfer format used with the CY2XP304. Two dummy bytes must be transferred before is at clk the first data byte. The CY2XP304 has only three bytes of from data latches to store information, and the third byte of data is reserved. Extra data will be ignored. ...
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... Serial Interface Programming for the CY2XP304 b7 b6 Data0 QCNTBYP SELPQ Data1 P<7> P<6> Data2 Reserved Reserved To program the CY2XP304 using the two-wire serial interface, set the SELPQ bit HIGH. The default setting of this bit is LOW. The P and Q values are determined by the following formulas final 7.. final 5 ...
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... Reference Functional Specifications Crystal Input The CY2XP304 receives its reference from an external crystal. Pin XIN is the reference crystal input, and pin XOUT is the reference crystal feedback. The parameters for the crystal are given on page 5 of this data sheet. The oscillator circuit requires external capacitors ...
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... Condition Non-functional Functional [1] Relative [1] Relative [1] Relative Functional Non-functional Functional Non-functional Functional Functional Assembled die Description Description s to reach minimum specified voltage DD Description CY2XP304 Min. Max. Unit –0.3 4.6 V 3.135 3.465 V V – –0 0 –0 0 ...
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... I = – INA, INAB –Input Description [5] Conditions CLK_SEL = 0 CLK_SEL = 1 f < 1GHz O 400-MHz 50% duty cycle Standard load Differential Operation 400-MHz 50% duty cycle Standard load Differential Operation 400-MHz 50% duty cycle Differential 20% to 80% CY2XP304 Min. Max. 0.4 1.9 0.68 0.9 |150| V – 1.995 V – 1 – 1.25 V – 0 ...
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... At 500-MHz frequency At 400-MHz frequency At 500-MHz frequency At 400-MHz frequency At 500-MHz frequency –PECL Clock Outputs: PLL Bypass Mode Conditions fo < 1.0 GHz 660 MHz 50% duty cycle Standard load PECL, 660MHz HSTL, <1 GHz Figure 5. ECL/LVPECL Output CY2XP304 Min. Max. Unit – – – – ...
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... DC,ERR PW+,i PW+,i+1 Figure 8. Cycle-to-cycle Duty Cycle Error t min t max – t JLT max min over many cycles Figure 9. Long-term Jitter CY2XP304 , is defined as the clock output DC ERR is defined as the long-term JLT Cycle i+1 tPW+,i tCYCLE, i Page ...
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... Figure 12. Low-Voltage Positive Emitter-Coupled Logic (LVPECL Document #: 38-07589 Rev. *B DUT PLL VTT VTT Figure 10. CY2XP304 AC Test Reference ...
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... Cypress against all charges. Operating Range Commercial, to 400 MHz Industrial, to 400 MHz 36-Lead VFBGA ( mm) BV36A Dimensions are in mm. CY2XP304 Operating Voltage 3.3V 3.3V 3.3V 3.3V 51-85149-*B ...
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... Document History Page Document Title: CY2XP304 High-Frequency Programmable PECL Clock Generation Module Document Number: 38-07589 Orig. of REV. ECN NO. Issue Date Change ** 129898 12/02/03 *A 235868 See ECN *B 247601 See ECN RGL/GGK Document #: 38-07589 Rev. *B RGL New Data Sheet RGL Updated Jitter spec based on the characterization report ...