AN2408 Freescale Semiconductor / Motorola, AN2408 Datasheet - Page 16

• Manufacturer Part Number: AN2408
• Description: Examples of HCS12 External Bus Design A Companion Note to AN2287/D
• Manufacturer: Freescale Semiconductor / Motorola

Example #6 — Word-Wide FLASH Interface with Banking – XCS/ECS Gated
Example #6 — Word-Wide FLASH Interface with Banking – XCS/ECS Gated
The following schematic demonstrates the interface to a 16-bit FLASH memory device to provide word
wide access. It uses expanded wide mode in order to support word access to the external device. It has
the addition of logic to support additional banks of external memories.
Comments:
16
PTK6/7
PTK0
PTK1
PTK2
PTK3
PTK4
PTK5
•
•
•
•
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RST
PE4
PE2
The XCS or ECS signal is required because the external device does not possess the active-high
chip-enable needed for using the ECLK signal to activate the external device. If the ECS signal is
implemented, the ROMON bit must be clear, as internal memory has precedence over external
memory. Because not all HCS12 Family members have the XCS signal, this design will not be
applicable in all instances. The system designer should assess the overall design to determine
applicability.
Byte access is not required, as the MCU will ignore the unneeded byte of a word transaction.
Therefore the LSTBR and ADDR0 signals are not implemented.
This interface will not be able to run at full bus speed, as the access time of external FLASH
memory has not reached the capabilities of internal memories. The HCS12 MCU supports as many
as three additional clock stretch cycles to support interfaces to these devices.
Data bus buffers will be required in this type of design due to the t
devices. They cannot three-state the data bus prior to the MCU next address access.
MCU ADDR[0]
MCU ADDR[1]
MCU ADDR[2]
MCU ADDR[3]
MCU ADDR[4]
MCU ADDR[5]
MCU ADDR[6]
MCU ADDR[7]
MCU ADDR[8]
MCU ADDR[9]
MCU ADDR[10]
MCU ADDR[11]
MCU ADDR[12]
MCU ADDR[13]
MCU ADDR[14]
MCU ADDR[15]
MCU_XADDR[14]
MCU_XADDR[15]
MCU_XADDR[16]
MCU_XADDR[17]
MCU_XADDR[18]
MCU_XADDR[19]
MCU ECS/XCS
MCU RESET
MCU ECLK
MCU R/W
Figure 16. Word-Wide FLASH Interface with Banking — XCS/ECS Gated
13
14
17
18
11
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
48
25
24
3
4
7
8
1
1
U23
74FCT373/SO
U24
74FCT16373/SO
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1LE
2LE
1OE
2OE
Examples of HCS12 External Bus Design, Rev. 2
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
ADDR[0]
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
ADDR[8]
ADDR[9]
ADDR[10]
ADDR[11]
ADDR[12]
ADDR[13]
ADDR[14]
ADDR[15]
XADDR[14]
XADDR[15]
XADDR[16]
XADDR[17]
XADDR[18]
XADDR[19]
2
3
1
U27A
74FCT139A/SO
A
B
G
Y 0
Y 1
Y 2
Y 3
4
5
6
7
VCC
OE*
11
10
42
41
40
39
38
37
36
35
34
33
14
44
43
12
9
8
7
6
5
4
3
U25
AM29F400AB/SO
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
BY TE
OE
RST
WE
CE
XADDR19
DQ15/A-1
RY /BY
1
0
0
0
0
DQ10
DQ11
DQ12
DQ13
DQ14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
R/W
X
0
0
1
1
15
17
19
21
24
26
28
30
16
18
20
22
25
27
29
31
2
EHOZ
ECLK
X
0
1
0
1
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
OE
1
1
1
1
0
timing of current FLASH
WE
1
1
0
1
1
11
12
13
14
16
17
19
20
22
23
2
3
5
6
8
9
A to B
A to B
A to B
A to B
B to A
DIR
U26
74FCT1624/SO
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
Freescale Semiconductor
1DIR
2DIR
1OE
2OE
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
24
48
25
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7