AN2497 Freescale Semiconductor / Motorola, AN2497 Datasheet - Page 6

• Manufacturer Part Number: AN2497
• Description: HCS08 Background Debug Mode versus HC08 Monitor Mode
• Manufacturer: Freescale Semiconductor / Motorola

AN2497/D
HCS08 Background Debug Controller (BDC) and Registers
6
Reset in Active BDM:
Normal Reset:
Read:
Write:
HCS08 Background Debug Mode versus HC08 Monitor Mode
The major benefit of the BDC is that it does not interfere with normal application
resources. It does not share any on-chip peripherals. The single BKGD
interface pin is a separate dedicated pin that is not accessible to user
programs. Background mode does not require high voltage for entry.
The BDC can access internal memory while the user program is running
because its hardware is independent of the CPU. The BDC steals a cycle as
soon as it can to access the memory. This has little impact on real-time
operation of the user’s program because a single bus cycle is stolen for each
memory access command which requires more than 500 BDM clock cycles. In
the HCS08, stealing a cycle means the CPU is suspended for a cycle so the
BDC can use the address and data buses to access the requested memory
location. However, the CPU suspension does not affect peripheral clocks, such
as the timer and serial clocks.
The HCS08 has two registers related to the BDC. One is called the BDC status
and control register (BDCSCR). (See
enable BDM (ENBDM) bit which permits the active background mode, the
communication clock option bit (CLKSW), and several BDC status bits
(BDMACT, WS, WSF, and DVF bits). The WS bit indicates whether the target
CPU is in WAIT or STOP mode. The WSF bit indicates whether a memory
access command failed due to the target CPU executing WAIT or STOP
instruction. The DVF bit indicates whether accessed data is valid. The
BDCSCR register is not in the user memory map. Since this register can only
be accessed by the debugger and not by the user program, it avoids the
possibility of enabling the BDM unintentionally while the user program is
running. To enable BDM (ENBDM = 1), a BDC WRITE_CONTROL command
has to be used.
ENBDM
Freescale Semiconductor, Inc.
Bit 7
Figure 3. BDC Status and Control Register
0
1
For More Information On This Product,
= Unimplemented or Reserved
BDMACT
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6
0
1
BKPTEN
5
0
0
FTS
4
0
0
Figure
CLKSW
3
0
1
3.) This register contains the
WS
2
0
0
WSF
1
0
0
MOTOROLA
Bit 0
DVF
0
0