AN2621 Freescale Semiconductor / Motorola, AN2621 Datasheet - Page 8

• Manufacturer Part Number: AN2621
• Description: MPC8220i PF300 Image Coprocessor Operation
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
The Screening Unit
The first three registers allow the application that initializes the screening function to define a
two-dimensional pixel array user space in which to work. The data held in these registers allow the
Screening Unit to map the user space to the processor’s linear address space. The last two registers allow
the starting phase of each threshold array tile to be aligned to other threshold array tiles or to the beginning
of the image. More detail about the location of the screener block control registers and the threshold array
value memory can be found in Chapter 27 of the MPC8220i Reference Manual. A flow chart of the
algorithm is presented in Appendix C, “Screening Unit Flow Chart,” and the C code representation of the
halftone screening algorithm as implemented in the PF300 is shown in Appendix D, “Screening Unit C
Code.”
The maximum tile size is limited by the amount of memory dedicated to this function. The implementation
in the MPC8220i is limited to 4 Kbytes. Applications developers have significant flexibility to configure
tiles of arbitrary dimensions that fit within this memory.
Each of up to four tiles can be configured with arbitrary X and Y dimensions with only two restrictions: each
tile must be at least two scan lines high (Y dimension), and all of the tiles together must not exceed the
4 Kbytes of available memory. There are no further restrictions. A separate, dedicated, memory is provided
for the tiles, which is mapped into the general purpose SDRAM address space so that the core processor can
read and write tile data.
If the target engine prints only a single color plane at a time (including monochrome printers) and it can
afford the overhead of reloading the screen tiles between processing of each color plane, then all 4 Kbytes
can be used for the single tile. In some applications, particularly when “FM” screens are employed, the same
tile can be used for each of the four-color planes so long as they are addressed out of phase from one another.
In this case the entire 4 Kbytes of memory can be dedicated to the single threshold array tile, and each color
plane can address it simultaneously in proper phase through appropriate initialization of the X and Y
dimension starting pixel phase registers.
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MPC8220i PF300 Image Coprocessor Operation
MOTOROLA
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