IDT72251L10J8 IDT, Integrated Device Technology Inc, IDT72251L10J8 Datasheet - Page 10
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IDT72251L10J8
Manufacturer Part Number
IDT72251L10J8
Description
IC FIFO SYNC 512X9 10NS 32PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet
1.IDT72211L10JG.pdf
(14 pages)
Specifications of IDT72251L10J8
Function
Synchronous
Memory Size
4.6K (512 x 9)
Access Time
10ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Configuration
Dual
Density
72Kb
Access Time (max)
6.5ns
Word Size
9b
Organization
8Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
PLCC
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
50mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Lead Free Status / Rohs Status
Not Compliant
Other names
72251L10J8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72251L10J8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
©
NOTE:
1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
NOTE:
1. When t
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
(If Applicable)
(If Applicable)
When
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Q
D
WCLK
t
WEN1
WEN2
REN1,
Q
RCLK
REN2
0
D
SKEW1
SKEW1
0
WCLK
WEN2
WEN1
- Q
REN1,
REN2
0
RCLK
- D
0
OE LOW
FF
- Q
- D
8
OE
8
EF
≥ minimum specification, t
< minimum specification, t
8
DATA IN OUTPUT REGISTER
8
t
DATA IN OUTPUT REGISTER
LOW
t
t
ENS
ENS
DS
t
ENS
DATA WRITE 1
t
NO WRITE
SKEW1
t
t
SKEW1
ENH
t
ENH
FRL
FRL
t
maximum = t
maximum = 2t
ENH
t
t
FRL
A
t
CLK
WFF
t
CLK
(1)
REF
+ t
+ t
SKEW1
SKEW1
t
t
ENS
ENS
t
DS
Figure 9. Empty Flag Timing
or t
Figure 8. Full Flag Timing
CLK
+ t
SKEW1
t
WFF
10
t
t
DATA READ
t
ENH
ENH
REF
t
A
t
t
ENS
ENS
t
t
ENS
DS
NO WRITE
DATA WRITE 2
t
ENH
t
A
t
t
t
ENH
SKEW1
ENH
t
DATA READ
SKEW1
COMMERCIAL AND INDUSTRIAL
t
WFF
NEXT DATA READ
t
TEMPERATURE RANGES
FFL
t
t
ENS
ENS
t
REF
(1)
(1)
(1)
OCTOBER 22, 2008
NO WRITE
2655 drw 11
2655 drw 10