AN2667 Freescale Semiconductor / Motorola, AN2667 Datasheet - Page 8

• Manufacturer Part Number: AN2667
• Description: Multi-Controller Hardware Development for the MPC5xx Family
• Manufacturer: Freescale Semiconductor / Motorola

Another possibility is that every MPC5xx in the system will take the RCW from its own
internal flash (RSTCONF=1 for all devices). This way may be preferable, since there is
no requirement to drive the external data bus with the RCW.
Once the system is built, but before any internal flash memories have been programmed,
the RESET configuration word should be taken as default (all the bits are 0). This gives
the user the opportunity to program the internal flash memories with their RCW. The
system must be reset once more in order for the new RCW to be taken. The following
bits of a RCW are of importance when configuring a multi-MPC5xx environment:
If reset is released simultaneously for all devices there will be an issue as the master
will have no capability of programming the slaves before they boot. This means that by
default the slaves will be configured as masters unless PRPM has been set in their
RCW.
The connection of HRESET and/or SRESET pins between the different devices in the
system is not required. Such a connection would mean simultaneous RESET for all
MPC5xx devices in the system. However, it may be useful to connect HRESET or
SRESET to an interrupt request(IRQx) input of the master in order to inform it about the
reset event.
3.5
A problem can arise if the CLKOUT signal from the master feeds the EXTCLK of the
slaves. The problem arises when the master changes its operation frequency to system
frequency. When this happens the PLL loses lock which means the slave devices have
no clock to execute their own code. An option used to overcome this would be to use an
oscillator module to feed all MPC5xx devices’ EXTCLK pin. The MODCK[1:3] pins for
the slave devices are set to 0x100 which selects extclk pin as a 1:1 clock source for the
slave. This enables the clock on the slave devices to synchronise to the clock on the
master device.
To overcome the above issues with reset and clocking an I/O port on the master should
be connected to PORESET of all the slave devices. Once the master PLL has locked
this port can be driven to release PORESET on all the slaves.
MOTOROLA
Clocking Strategy
– PRPM
– EARB
– ISB0:2
– IP
– ETRE
– OERC
– FLEN
Multi-Controller Hardware Development for the MPC5xx Family
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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