SP8691 Plessey, SP8691 Datasheet
SP8691
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SP8691 Summary of contents
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... The SP8690 and SP8691 are low power ECL variable modulus dividers, with both ECL10K and TTL/CMOS compatible outputs. They divide by the lower division ratio when either of the ECL control inputs, PE1 or PE2 the high state and by the higher ratio when both are low (or open circuit). ...
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... Guaranteed but not tested. 7. The open collector output is not recommended for use at output frequencies above 15MHz Fig. 3 Functional diagram (SP8691) Value Units Symbol Min. Max. f 200 MHz Input = 400-800mV p-p MAX f 40 MHz Input = 400-800mV p-p MIN ...
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... Fig. 7 Typical input impedance. Test conditions: Supply Voltage = 5.0V, Ambient Temperature = 25°C. Frequencies in MHz, impedances normalised to 50Ω Fig. 4 Timing diagram, SP8690 Fig. 5 Timing diagram, SP8691 GUARANTEED * OPERATING WINDOW 50 100 150 200 INPUT FREQUENCY (MHz 0 0.2 ...
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... O 10k 10k DIVIDE BY 10/11 (SP8690) 8/9 (SP8691 BIAS 8 Fig. 9 Typical application showing interfacing. 5. The PE inputs are ECLIII/10K compatible and include internal 10kΩ pulldown resistors. Unused inputs can therefore be left open circuit. 6. The input impedance of the SP8690/1 varies as a function of frequency ...
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NOTES 5 ...
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... SP8690/SP8691 PACKAGE DETAILS Dimensions are shown thus: mm (in). 5·59/7·87 (0·220/0·310) 1·14/1·65 (0·045/0·065) 5·08/(0·20) MAX SEATING PLANE 0·36/0·58 (0·014/0·23) HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 ...