MD1810 Supertex, Inc., MD1810 Datasheet - Page 6

• Manufacturer Part Number: MD1810
• Description: High Speed Quad Mosfet Driver
• Manufacturer: Supertex, Inc.

Application Information
For proper operation of the MD1810, low inductance bypass
capacitors should be used on the various supply pins. The
GND pin should be connected to the logic ground. The INA,
INB INC, IND, and OE pins should be connected to a logic
source with a swing of GND to V
Good trace practices should be followed corresponding to the
desired operating speed. The internal circuitry of the MD1810
is capable of operating up to 100MHz, with the primary speed
limitation being the loading effects of the load capacitance.
Because of this speed and the high transient currents that
result with capacitive loads, the bypass capacitors should
be as close to the chip pins as possible. Unless the load
specifically requires bipolar drive, the V
have low inductance feed-through connections directly to a
ground plane. If these voltages are not zero, then they need
bypass capacitors in a manner similar to the positive power
supplies. The power connection V
bypass capacitor to the ground plane with short leads and
decoupling components to prevent resonance in the power
leads.
The voltages of VH and VL decide the output signal levels.
These two pins can draw fast transient currents of up to
2.0A, so they should be provided with an appropriate bypass
capacitor located next to the chip pins. A ceramic capacitor
LL
, where V
DD
should have a ceramic
SS
, and V
LL
is 1.2 to 5.0 volts.
L
pins should
6
of up to 1.0µF may be appropriate, with a series ferrite bead
to prevent resonance in the power supply lead coming to
the capacitor. Pay particular attention to minimizing trace
lengths, current loop area and using sufficient trace width to
reduce inductance. Surface mount components are highly
recommended. Since the output impedance of this driver is
very low, in some cases it may be desirable to add a small
series resistance in series with the output signal to obtain
better waveform transitions at the load terminals. This will of
course reduce the output voltage slew rate at the terminals
of a capacitive load.
Pay particular attention that parasitic couplings are minimized
from the output to the input signal terminals. The parasitic
feedback may cause oscillations or spurious waveform
shapes on the edges of signal transitions. Since the input
operates with signals down to 1.2V even small coupled
voltages may cause problems. Use of a solid ground plane
and good power and signal layout practices will prevent this
problem. Be careful that a circulating ground return current
from a capacitive load cannot react with common inductance
to cause noise voltages in the input logic circuitry.
MD1810