IDT72225LB10PF IDT, Integrated Device Technology Inc, IDT72225LB10PF Datasheet - Page 9

IC FIFO 1024X18 SYNC 10NS 68TQFP

IDT72225LB10PF

Manufacturer Part Number
IDT72225LB10PF
Description
IC FIFO 1024X18 SYNC 10NS 68TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT72225LB10PF

Function
Synchronous
Memory Size
18.4K (1K x 18)
Access Time
10ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
68-TQFP, 68-VQFP
Configuration
Dual
Density
18Kb
Access Time (max)
6.5ns
Word Size
18b
Organization
1Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
60mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
72225LB10PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72225LB10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72225LB10PF
Manufacturer:
IDT
Quantity:
252
Part Number:
IDT72225LB10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72225LB10PF8
Manufacturer:
IDT
Quantity:
252
Part Number:
IDT72225LB10PFB
Manufacturer:
IDT
Quantity:
271
NOTE:
1. t
NOTE:
1. t
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Q
D
edge of RCLK and the rising edge of WCLK is less than t
0
WCLK
edge of WCLK and the rising edge of RCLK is less than t
SKEW1
RCLK
WCLK
0
SKEW2
RCLK
- Q
- D
17
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
17
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising
t
ENS
t
OLZ
t
SKEW1
t
t
ENH
t
CLKH
CLKH
(1)
t
WFF
t
t
A
REF
t
SKEW1
OE
SKEW2
t
CLK
, then FF may not change state until the next WCLK edge.
, then EF may not change state until the next RCLK edge.
t
DATA IN VALID
CLK
Figure 5. Write Cycle Timing
Figure 6. Read Cycle Timing
NO OPERATION
t
SKEW2
t
t
CLKL
t
CLKL
DS
(1)
t
ENS
9
TM
VALID DATA
t
t
ENH
DH
t
t
REF
WFF
t
OHZ
COMMERCIAL AND INDUSTRIAL
NO OPERATION
TEMPERATURE RANGES
OCTOBER 22, 2008
2766 drw 07
2766 drw 08

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