IDT72V263L15PF8 IDT, Integrated Device Technology Inc, IDT72V263L15PF8 Datasheet - Page 41

• Manufacturer Part Number: IDT72V263L15PF8
• Description: IC FIFO 8192X18 15NS 80QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L15PF8

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 18/9Bit
• Organization: 8Kx18/16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 30@9BIT/35@18BITmA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L15PF8

SYSTEM INTERFACE PARAMETERS
NOTE:
1. 50pf loading on external output signals.
TRST
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
Data Output Hold
TDI/
TMS
TDO
TCK
Data Output
Parameter
Data Input
t
DO
Symbol Test Conditions
t
3
t
DOH
t
t
= Max
DH
DS
t
5
(1)
t
t
t
rise=3ns
fall=3ns
1
t
6
t
t
4
t
DS
TCK
Min.
t
10
10
0
DH
-
IDT72V223
IDT72V233
IDT72V243
IDT72V253
IDT72V263
IDT72V273
IDT72V283
IDT72V293
Figure 31. Standard JTAG Timing
Notes to diagram:
t1 = t
t2 = t
t3 = t
t4 = t
t5 = t
t6 = t
t
Max. Units
2
20
-
-
-
TCKHIGH
TCKFALL
TCKRise
RST
RSR
TCKLOW
(reset recovery)
(reset pulse width)
ns
ns
ns
TM
41
NARROW BUS FIFO
NOTE:
1. Guaranteed by design.
(V
JTAG AC ELECTRICAL
CHARACTERISTICS
JTAG Clock Input Period t
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
JTAG Reset Recovery
CC
TM
NARROW BUS FIFO
= 3.3V
Parameter
±
5%; Tcase = 0°C to +85°C)
Symbol
t
t
t
t
t
t
TCKHIGH
TCK
TCKLOW
TCKRise
TCKFall
RST
RSR
COMMERCIAL AND INDUSTRIAL
Conditions Min. Max. Units
t
Test
DO
-
-
-
-
-
-
-
TEMPERATURE RANGES
FEBRUARY 11, 2009
100
40
40
50
50
-
-
TDO
5
5
-
-
-
-
-
(1)
(1)
4666 drw34
ns
ns
ns
ns
ns
ns
ns