MCP2030 Microchip Technology Inc., MCP2030 Datasheet - Page 52
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MCP2030
Manufacturer Part Number
MCP2030
Description
Three-channel Analog Front-end Device
Manufacturer
Microchip Technology Inc.
Datasheet
1.MCP2030.pdf
(66 pages)
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MCP2030
REGISTER 5-2:
REGISTER 5-3:
DS21981A-page 52
bit 8
bit 7
bit 6-1
bit 0
bit 8-7
bit 6-1
bit 0
Legend:
R = Readable bit
-n = Value at POR
Legend:
R = Readable bit
-n = Value at POR
RSSIFET: Pull-down MOSFET on LFDATA pad bit (controllable by user in the RSSI mode only)
1 = Pull-down RSSI MOSFET on
0 = Pull-down RSSI MOSFET off
CLKDIV: Carrier Clock Divide-by bit
1 = Carrier clock/4
0 = Carrier clock/1
LCYTUN<5:0>: LCY Tuning Capacitance bit
000000 = +0 pF (Default)
111111 = +63 pF
R2PAR: Register 2 Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
bit 8
bit 8
DATOUT<1:0>: LFDATA Output type bit
00 = Demodulated output
01 = Carrier clock output
10 = RSSI output
11 = RSSI output
LCXTUN<5:0>: LCX Tuning Capacitance bit
000000 = +0 pF (Default)
111111 = +63 pF
R1PAR: Register 1 Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
RSSIFET
DATOUT
CONFIGURATION REGISTER 1 (ADDRESS: 0001)
CONFIGURATION REGISTER 2 (ADDRESS: 0010)
R/W-0
R/W-0
1
DATOUT
CLKDIV
R/W-0
R/W-0
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
0
:
:
LCXTUN5 LCXTUN4 LCXTUN3 LCXTUN2 LCXTUN1 LCXTUN0
LCYTUN5 LCYTUN4 LCYTUN3 LCYTUN2 LCYTUN1 LCYTUN0
R/W-0
R/W-0
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
© 2005 Microchip Technology Inc.
R/W-0
R/W-0
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R1PAR
R2PAR
R/W-0
R/W-0
bit 0
bit 0