MCP7940N Microchip Technology Inc., MCP7940N Datasheet - Page 14

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MCP7940N

Manufacturer Part Number
MCP7940N
Description
Manufacturer
Microchip Technology Inc.
Datasheet

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MCP7940N
5.0
The MCP7940N has battery-backed SRAM. The
SRAM is arranged as 64 x 8 bytes and is retained when
the V
is present and enabled.
5.1
FIGURE 5-1:
FIGURE 5-2:
The 64 bytes of user SRAM are at location 0x20h and
can be accessed during an RTCC update. Upon POR
the SRAM will be in an undefined state.
DS25010A-page 14
Note:
CC
supply is removed, provided the V
ON BOARD MEMORY
SRAM
Entering an address past 5F for an SRAM
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
operation will result in the MCP7940N not
acknowledging the address.
SRAM/RTCC BYTE WRITE
SRAM/RTCC MULTIPLE BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S 1 1 0 1
CONTROL
BYTE
1 1 1
S 1 1 0 1
S
T
A
R
T
BAT
0
A
C
K
CONTROL
supply
x
BYTE
ADDRESS
1 1 1
BYTE
0
A
C
K
x
ADDRESS
A
C
K
BYTE
DATA BYTE 0
A
C
K
A
C
K
DATA
 2011 Microchip Technology Inc.
DATA BYTE N
A
C
K
S
T
O
P
P
A
C
K
S
T
O
P
P

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