XC3064A-7PQ166C Xilinx, Inc., XC3064A-7PQ166C Datasheet
XC3064A-7PQ166C
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XC3064A-7PQ166C Summary of contents
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... Excellent reliability record Max Logic Device Gates XC3020A, 3020L, 3120A 1,500 XC3030A, 3030L, 3130A 2,000 XC3042A, 3042L, 3142A, 3142L 3,000 XC3064A, 3064L, 3164A 4,500 XC3090A, 3090L, 3190A, 3190L 6,000 XC3195A 7,500 November 9, 1998 (Version 3.1) 0 XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) ...
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XC3000 Series Field Programmable Gate Arrays Introduction XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of ...
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R Improvements in the XC3000A and XC3000L Families The XC3000A and XC3000L families offer the following enhancements over the popular XC3000 family: The XC3000A and XC3000L families have additional inter- connect resources to drive the I-inputs of TBUFs driving horizontal ...
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XC3000 Series Field Programmable Gate Arrays Detailed Functional Description The perimeter of configurable Input/Output Blocks (IOBs) provides a programmable interface between the internal logic array and the device package pins. The array of Con- figurable Logic Blocks (CLBs) performs user-specified ...
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R Read or Write Data Figure 3: Static Configuration Memory Cell loaded with one bit of configuration program and con- trols one program selection in the Field Programmable Gate Array. The memory cell outputs Q and Q use ...
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XC3000 Series Field Programmable Gate Arrays The input-buffer portion of each IOB provides threshold detection to translate external signals applied to the pack- age pin to internal logic levels. The global input-buffer threshold of the IOBs can be programmed to ...
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R Configurable Logic Block The array of CLBs provides the functional elements from which the user’s logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. For example, the XC3020A has 64 such blocks ...
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XC3000 Series Field Programmable Gate Arrays Flexible routing allows use of common or individual CLB clocking. The combinatorial-logic portion of the CLB uses look-up table to implement Boolean functions. Variables selected from the five logic inputs ...
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R Count Enable Parallel Enable Clock Dual Function of 4 Variables D0 D1 Function of 5 Variables D2 Function of 6 Variables Figure 7: Counter. The modulo-8 binary counter with parallel enable and clock enable uses one combinatorial logic block ...
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XC3000 Series Field Programmable Gate Arrays Figure 9: Design Editor Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect PIPs are directional. 7-12 R ...
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R Figure 10: FPGA General-Purpose Interconnect. Composed of a grid of metal segments that may be inter- connected through switch matrices to form networks for CLB and IOB inputs and outputs. Figure 11: Switch Matrix Interconnection Options for Each Pin. ...
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XC3000 Series Field Programmable Gate Arrays Global Buffer Direct Input * Unbonded IOBs (6 Places) Figure 13: XC3020A Die-Edge IOBs. The XC3020A die-edge IOBs are provided with direct access to adjacent CLBs. 7-14 Global Buffer Inerconnect Alternate Buffer Direct Input ...
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R Longlines The Longlines bypass the switch matrices and are intended primarily for signals that must travel a long distance, or must have minimum skew among multiple destinations. Longlines, shown in Figure 14, run vertically and horizon- tally the height ...
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XC3000 Series Field Programmable Gate Arrays Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-state buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left ...
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R A buffer in the upper left corner of the FPGA chip drives a global net which is available to all K inputs of logic blocks. Using the global buffer for a clock signal provides a skew-free, high fan-out, synchronized ...
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XC3000 Series Field Programmable Gate Arrays Crystal Oscillator Figure 18 also shows the location of an internal high speed inverting amplifier that may be used to implement an on-chip crystal oscillator associated with the auxiliary buffer in the ...
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... Cycles for the XC3020A—130 to 400 s ~ 250 Cycles for the XC3030A—165 to 500 s ~ 290 Cycles for the XC3042A—195 to 580 s ~ 330 Cycles for the XC3064A—220 to 660 s ~ 375 Cycles for the XC3090A—250 to 750 s shows the state sequences. At the end ...
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... K 4) where function of DONE and RESET timing selected. An additional 8 is Figure Header Program Data Repeated for Each Logic Cell Array in a Daisy Chain X5300_01 XC3090A XC3064A XC3090L XC3064L XC3190A XC3164A XC3190L XC3195A 3,500 to 4,500 5,000 to 6,000 6,500 to 7,500 224 ...
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R a synchronous start-up sequence and become operational. See Figure 22. Two CCLK cycles after the completion of loading configuration data, the user I/O pins are enabled as configured. As selected, the internal user-logic RESET is released either one clock ...
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XC3000 Series Field Programmable Gate Arrays be used to drive the remaining unused routing, as that might affect timing of user nets. Tie can be omitted for quick breadboard iterations where a few additional milliamps of Icc are acceptable. The ...
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R Special Configuration Functions The configuration data includes control over several spe- cial functions in addition to the normal user logic functions and interconnect. • Input thresholds • Readback disable • DONE pull-up resistor • DONE timing • RESET timing ...
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XC3000 Series Field Programmable Gate Arrays RESET Timing As with DONE timing, the timing of the release of the inter- nal reset can be controlled to occur either a CCLK cycle before, or after, the outputs going active. See This ...
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R Configuration Timing This section describes the configuration modes in detail. Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the DIN input. Each rising edge of the ...
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XC3000 Series Field Programmable Gate Arrays CCLK (Output Serial Data In Serial DOUT n – 3 (Output) Description Data In setup CCLK Data In hold Notes power-up, V must rise from 2 ...
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R Master Parallel Mode In Master Parallel mode, the lead FPGA directly addresses an industry-standard byte-wide EPROM and accepts eight data bits right before incrementing (or decrementing) the address outputs. The eight data bits are serialized in the lead FPGA, ...
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XC3000 Series Field Programmable Gate Arrays A0-A15 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description To address valid To data setup RCLK To data hold RCLK High RCLK Low Notes power-up, V must rise from 2.0 V ...
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R Peripheral Mode Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS inputs to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a ...
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XC3000 Series Field Programmable Gate Arrays WRITE TO FPGA WS, CS0, CS1 CS2 T D0-D7 CCLK RDY/BUSY DOUT Description Effective Write time required (Assertion of CS0, CS1, CS2, WS) DIN Setup time required WRITE DIN Hold time required RDY/BUSY delay ...
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R Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input(s) of the FPGA(s). The serial configuration bitstream must be available at the DIN input of the lead FPGA a short set-up time before each rising ...
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XC3000 Series Field Programmable Gate Arrays DIN 1 T DCC CCLK DOUT (Output) Description To DOUT DIN setup CCLK DIN hold High time Low time (Note 1) Frequency Notes: 1. The max limit of CCLK Low time is caused by ...
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R Program Readback Switching Characteristics DONE/PROG (OUTPUT) RTRIG (M0) 4 CCLK( CCRD HI-Z M1 Input/ RDATA Output Description RTRIG RTRIG High RTRIG setup RDATA delay CCLK High time Low time Notes: 1. During Readback, CCLK frequency may not ...
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XC3000 Series Field Programmable Gate Arrays General XC3000 Series Switching Characteristics RESET M0/M1/ DONE/PROG INIT User State (Output) PWRDWN V (Valid) CC Description M0, M1, M2 setup time required RESET (2) M0, M1, M2 hold ...
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... CLB delay by only 10%. Clocks can be distributed with two low-skew clock distribution networks. The tools in the Development System used to place and route a design in an XC3000 FPGA automatically calculate the actual maximum worst-case delays along each signal path. This timing information can be back-annotated to the design’ ...
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XC3000 Series Field Programmable Gate Arrays 1.00 0.80 0.60 0.40 0.20 – 55 – 40 – 20 Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations 300 250 200 150 100 XC3100A-3 50 XC3000A--6 0 ...
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R Dynamic Power Consumption One CLB driving three local interconnects One global clock buffer and clock line One device output with load Power Consumption The Field Programmable Gate Array exhibits the low power consumption characteristic of CMOS ...
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XC3000 Series Field Programmable Gate Arrays Pin Descriptions Permanently Dedicated Pins V CC Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight (depending on package type) connections ...
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R AND of several slave mode devices, a hold-off signal for a master mode device. After configuration this pin becomes a user-programmable I/O pin. BCLKIN This is a direct CMOS level input to the alternate clock buffer (Auxiliary Buffer) in ...
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... INIT is an open drain output during configuration. (I) Represents an input. ** Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown. *** Peripheral mode and master parallel mode are not supported in the PC44 package. **** Pin assignments for the XC3195A PQ208 differ from those shown. ...
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R XC3000A Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3000A Operating Conditions Symbol Supply ...
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XC3000 Series Field Programmable Gate Arrays XC3000A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum ...
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R XC3000A CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...
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XC3000 Series Field Programmable Gate Arrays XC3000A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) ...
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R XC3000A IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...
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XC3000 Series Field Programmable Gate Arrays XC3000A IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O ...
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R XC3000L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3000L Operating Conditions Symbol V ...
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XC3000 Series Field Programmable Gate Arrays XC3000L Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum ...
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R XC3000L CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...
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XC3000 Series Field Programmable Gate Arrays XC3000L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) ...
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R XC3000L IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...
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XC3000 Series Field Programmable Gate Arrays XC3000L IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O ...
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R XC3100A Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3100A Operating Conditions Symbol Supply ...
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XC3000 Series Field Programmable Gate Arrays XC3100A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum ...
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R XC3100A CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...
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XC3000 Series Field Programmable Gate Arrays XC3100A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) ...
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R XC3100A IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...
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XC3000 Series Field Programmable Gate Arrays XC3100A IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O ...
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R XC3100L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3100L Operating Conditions Symbol V ...
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XC3000 Series Field Programmable Gate Arrays XC3100L Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum ...
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R XC3100L CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...
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XC3000 Series Field Programmable Gate Arrays XC3100L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) ...
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R XC3100L IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...
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XC3000 Series Field Programmable Gate Arrays XC3100L IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O ...
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R XC3000 Series Pin Assignments Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 208. Each chip is offered in several package types ...
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 64-Pin Plastic VQFP Pinouts XC3000A, XC3000L, and XC3100A families have identical pinouts Pin No. XC3030A 1 A0-WS-I/O 2 A1-CS2-I/O 3 A2-I/O 4 A3-I/O 5 A4-I/O 6 A14-I/O 7 A5-I/O 8 GND 9 ...
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R XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts 68 PLCC XC3020A, XC3030A, XC3030A XC3020A XC3042A 10 10 PWRDN 11 11 TCLKIN-I/O 12 — ...
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... XTL2(IN)-I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin definition than XC3020A/XC3030A/XC3042A. 7-68 ...
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R XC3000 Series 100-Pin QFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin No. XC3020A TQFP XC3030A PQFP VQFP XC3042A 16 13 GND 17 14 A13-I A6-I A12-I A7-I ...
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... N10 I/O P10 I/O M9 I/O N9 CS0-I/O I/O P9 I/O P8 INIT-I/O N8 VCC P7 GND M8 I/O M7 I/O N7 I/O P6 CS1-I/O I/O N6 I/O P5 I/O M6 I/O N5 I/O* P4 I/O P3 I/O M5 I/O N4 RDY/BUSY-RCLK-I/O I/O P2 XTL2(IN)-I/O N3 GND N2 D0-DIN-I/O PGA Pin XC3042A Number XC3064A M3 DOUT-I/O VCC P1 CCLK M4 VCC D7-I/O L3 GND M2 A0-WS-I/O I/O N1 A1-CS2-I/O I/O M1 I/O D6-I/O K3 I/O I/O L2 A2-I/O I/O* L1 A3-I/O I/O K2 I/O I/O J3 I/O D5-I/O K1 A15-I/O J2 A4-I/O I/O* J1 I/O* I/O* H1 A14-I/O D4-I/O H2 A5-I/O I/O H3 GND VCC G3 VCC ...
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... I/O 78 D6-I/O 79 I/O 80 I/O* 81 I/O 82 I/O 83 I/O* 84 D5-I/O 85 CS0-I/O 86 I/O* 87 I/O* 88 D4-I/O 89 I/O 90 VCC 91 GND 92 D3-I/O 93 CS1-I/O 94 I/O* 95 I/O* 96 D2-I/O XC3042A Pin XC3064A Number XC3090A 97 I/O 98 I/O 99 I/O* 100 I/O 101 I/O* 102 D1-I/O 103 RDY/BUSY-RCLK-I/O 104 I/O 105 I/O 106 D0-DIN-I/O 107 DOUT-I/O 108 CCLK 109 VCC 110 GND -I/ 111 A0-WS O 112 A1-CS2-I/O 113 I/O 114 I/O 115 ...
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... I/ I/ M1-RDATA 80 Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed IOBs are default slew-rate limited. * Indicates unconnected package pins (18) for the XC3064A. 7-72 XC3064A, XC3090A, PQFP Pin XC3064A, XC3090A, XC3195A Number XC3195A GND 81 M0–RTRIG ...
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R XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA Pin PGA Pin XC3090A, XC3195A Number Number B2 PWRDN D13 D4 TCLKIN-I/O B14 B3 I/O C14 C4 I/O B15 B4 I/O ...
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 176-Pin TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin Pin XC3090A Number Number 1 PWRDWN 45 2 TCLKIN I/O 49 ...
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R XC3000 Series 208-Pin PQFP Pinouts XC3000A, and XC3000L families have identical pinouts Pin Number XC3090A Pin Number 1 – GND 54 3 PWRDWN 55 4 TCLKIN ...
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XC3000 Series Field Programmable Gate Arrays XC3195A PQ208 Pinouts Pin Description PQ208 A9-I/O 206 A10-I/O 205 I/O 204 I/O 203 I/O 202 I/O 201 RDY/BUSY-RCLK-I/O A8-I/O 200 A11-I/O 199 I/O 198 I/O 197 I/O 196 I/O 194 A7-I/O 193 A12-I/O ...
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... Pins Plast. Plast. Plast. Type PLCC VQFP PLCC Code PC44 VQ64 PC68 -7 CI XC3020A - XC3030A - XC3042A -6 -7 XC3064A -6 -7 XC3090A -6 XC3020L -8 XC3030L -8 CI XC3042L -8 XC3064L -8 XC3090L - XC3120A - - ...
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XC3000 Series Field Programmable Gate Arrays Pins Plast. Plast. Plast. Type PLCC VQFP PLCC Code PC44 VQ64 PC68 XC3142L XC3190L Notes Commercial, T Number of Available I/O Pins Max I/O XC3020A/XC3120A 64 XC3030A/XC3130A 80 XC3042A/3142A ...