IDT72V255LA10PFG IDT, Integrated Device Technology Inc, IDT72V255LA10PFG Datasheet - Page 21
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IDT72V255LA10PFG
Manufacturer Part Number
IDT72V255LA10PFG
Description
IC FIFO SS 8192X18 10NS 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V255LA10TFG.pdf
(27 pages)
Specifications of IDT72V255LA10PFG
Function
Synchronous
Memory Size
144K (8K x 18)
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
144Kb
Access Time (max)
6.5ns
Word Size
18b
Organization
8Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
72V255LA10PFG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V255LA10PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V255LA10PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D –2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
3. OE = LOW
4. W
5. OR goes LOW at 60 ns + 2 RCLK cycles + t
WCLK
NOTE:
1. X = 12 for the IDT72V255LA and X = 13 for the IDT72V265LA.
8,192 x 18, 16,384 x 18
Q
WCLK
procedure. D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
SEN
RCLK
0
WEN
REN
LD
1
PAE
PAF
- Q
SI
, W
OR
RT
HF
2
n
, W
t
3
ENS
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
LDS
t
ENS
DS
t
ENS
t
RTS
t
RTS
REF
t
t
ENH
LDH
.
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
SKEW4
1
Figure 12. Retransmit Timing (FWFT Mode)
2
t
PAF
1
W
x+1
BIT X
21
(1)
BIT 0
2
t
PAE
FULL OFFSET
3
COMMERCIAL AND INDUSTRIAL
t
A
t
ENH
t
REF
(5)
TEMPERATURE RANGES
W
1
(4)
BIT X
OCTOBER 22, 2008
t
t
t
t
LDH
LDH
LDH
ENH
(1)
W
4
2
t
A
4672 drw 16
t
ENH
4672 drw15
W
3