IDT72V261LA10PF IDT, Integrated Device Technology Inc, IDT72V261LA10PF Datasheet - Page 9
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IDT72V261LA10PF
Manufacturer Part Number
IDT72V261LA10PF
Description
IC FIFO SS 8192X18 10NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V271LA10PFG.pdf
(27 pages)
Specifications of IDT72V261LA10PF
Function
Synchronous
Memory Size
144K (8K x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
144Kb
Access Time (max)
6.5ns
Word Size
9b
Organization
16Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V261LA10PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V261LA10PF
Manufacturer:
SHARP
Quantity:
44
Company:
Part Number:
IDT72V261LA10PF
Manufacturer:
IDT
Quantity:
1 150
Company:
Part Number:
IDT72V261LA10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V261LA10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
LD
0
0
0
X
1
1
1
8
8
8
8
IDT72V261LA ⎯ 16,384 x 9 − BIT
WEN
5
5
X
7
0
1
1
1
0
1
7
3FFH if LD is HIGH at Master Reset
3FFH if LD is HIGH at Master Reset
07FH if LD is LOW at Master Reset
07FH if LD is LOW at Master Reset
EMPTY OFFSET (MSB) REG.
EMPTY OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
FULL OFFSET (MSB) REG.
REN
X
1
0
1
1
0
1
DEFAULT VALUE
DEFAULT VALUE
Figure 4. Programmable Flag Offset Programming Sequence
00H
00H
Figure 3. Offset Register Location and Default Values
SEN
1
1
X
X
X
1
0
WCLK
X
X
X
X
0
0
0
0
9
8
8
8
8
IDT72V271LA ⎯ 32,768 x 9 − BIT
RCLK
X
X
X
X
X
6
6
7
7
3FFH if LD is HIGH at Master Reset
3FFH if LD is HIGH at Master Reset
07FH if LD is LOW at Master Reset
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
28 bits for the 72V261LA
30 bits for the 72V271LA
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
No Operation
Write Memory
Read Memory
No Operation
07FH if LD is LOW at Master Reset
Ending with Full Offset (MSB)
EMPTY OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
EMPTY OFFSET (MSB) REG.
FULL OFFSET (MSB) REG.
DEFAULT VALUE
DEFAULT VALUE
COMMERCIAL AND INDUSTRIAL
00H
00H
Selection
TEMPERATURE RANGES
JANUARY 30, 2009
4673 drw 06
0
0
0
0
4673 drw 07