AD8065 AD8066 Analog Devices, AD8065 AD8066 Datasheet - Page 17

• Manufacturer Part Number: AD8065 AD8066
• Description: High Performance, 145 MHz Fast FET Op Amps
• Manufacturer: Analog Devices

The closed-loop bandwidth is inversely proportional to the
noise gain of the op amp circuit, (R
model is accurate for noise gains above 2. The actual bandwidth
of circuits with noise gains at or below 2 will be higher than
those predicted with this model
poles in the frequency response of the real op amp.
Figure 4 shows a voltage feedback amplifier’s dc errors. For
both inverting and noninverting configurations
The voltage error due to I
(though with the AD8065 input currents at less than 20 pA
overtemperature, this is likely not a concern). To include
common-mode and power supply rejection effects, total V
be modeled as
V
the change in power supply from nominal conditions. PSR is the
power supply rejection. V
voltage from nominal conditions. CMR is the common-mode
rejection.
Wideband Operation
Test Circuits 1, 2, and 3 show the circuits used for wideband
characterization for gains of +1, +2, and –1. Source impedance at
the summing junction (R
loop response with the amplifier’s input capacitance of 6.6 pF.
This can cause peaking and ringing if the time constant formed is
too low. Feedback resistances of 300 W to 1 kW are recommended,
since they will not unduly load down the amplifier and the time
constant formed will not be too low. Peaking in the frequency
response can be compensated with a small capacitor (C
parallel with the feedback resistor, as illustrated in TPC 9. This
shows the effect of different feedback capacitances on the peaking
and bandwidth for a noninverting G = +2 amplifier.
For the best settling times and the best distortion, the impedances
at the AD8065/AD8066 input terminals should be matched. This
minimizes nonlinear common-mode capacitive effects that can
degrade ac performance.
REV. B
V (error)
OS nom
O
Figure 4. Voltage Feedback Amplifier DC Errors
is the offset voltage specified at nominal conditions. DV
=
V
I
R
I
b+
G
¥
V
OS
R
R
S
S
=
Ê
Á
Ë
+V
V
R
F
OS
OS nom
G
b+
R
R
CM
–
+
G
G
and I
) will form a pole in the amplifier’s
R
is the change in common-mode
+
F
due to the influence of other
ˆ
˜ -
¯
b–
PSR
D
V
F
is minimized if R
S
I
+ R
b-
I
I
b
b
+
+
–
R
¥
G
D
F
CMR
)/R
R
V
F
A
CM
G
+
. This simple
V
OS
Ê
Á
Ë
S
R
= R
V
G
F
) in
O
R
OS
+
F
G
R
can
R
S
F
G
is
ˆ
˜
¯
–17–
Actual distortion performance depends on a number of variables:
Also see TPCs 13 to 17. The lowest distortion will be obtained with
the AD8065 used in low gain inverting applications, since this
eliminates common-mode effects. Higher closed-loop gains
result in worse distortion performance.
Input Protection
The inputs of the AD8065/AD8066 are protected with back-to-
back diodes between the input terminals as well as ESD diodes to
either power supply. This results in an input stage with picoamps
of input current that can withstand up to 1500 V ESD events
(human body model) with no degradation.
Excessive power dissipation through the protection devices will
destroy or degrade the performance of the amplifier. Differential
voltages greater than 0.7 V will result in an input current of
approximately (|V
in series with the inputs. For input voltages beyond the positive
supply, the input current will be approximately (V
Beyond the negative supply, the input current will be about
(V
subjected to sustained differential voltages greater than 0.7 V or
to input voltages beyond the amplifier power supply, input
current should be limited to 30 mA by an appropriately sized
input resistor (R
Thermal Considerations
With 24 V power supplies and 6.5 mA quiescent current, the
AD8065 dissipates 156 mW with no load. The AD8065/AD8066
dissipate 312 mW. This can lead to noticeable thermal effects,
especially in the small SOT-23-5 (thermal resistance of 160 C W).
V
17 mV ∞C, so it can change up to 0.425 mV due to warm-up
effects for an AD8065/AD8066 in a SOT-23-5 package on 24 V.
I
I
a single 5 V supply.
Heavy loads will increase power dissipation and raise the chip
junction temperature as described in the Maximum Power
Dissipation section. Care should be taken to not exceed the rated
power dissipation of the package.
b
b
OS
∑ The closed-loop gain of the application
∑ Whether it is inverting or noninverting
∑ Amplifier loading
∑ Signal frequency and amplitude
∑ Board layout
increases by a factor of 1.7 for every 10 C rise in temperature.
will be close to 5 times higher at 24 V supplies as opposed to
I
– V
temperature drift is trimmed to guarantee a max drift of
FOR LARGE | V
R
I
>
EE
(| V + – V
V
I
+ 0.7)/R
Figure 5. Current Limiting Resistor
30mA
–
| – 0.7V)
+
I
) as shown in Figure 5.
– V
R
+
I
I
–
. If the inputs of the amplifier are to be
– V
|
–
|– 0.7 V)/R
AD8065
AD8065/AD8066
I
, where R
R
R
I
I
>
>
V
O
(V I – V
(V I – V
FOR V
SUPPLY VOLTAGES
I
is the resistance
30mA
30mA
I
EE
EE
– V
I
BEYOND
+ 0.7V)
– 0.7V)
CC
– 0.7)/R
I
.