MIC2589 Micrel Semiconductor, MIC2589 Datasheet - Page 11

• Manufacturer Part Number: MIC2589
• Description: (MIC2589 / MIC2595) SINGLE-CHANNEL NEGATIVE HIGH VOLTAGE HOT SWAP POWER CONTROLLERS/SEQUENCERS
• Manufacturer: Micrel Semiconductor

Functional Description
Hot Swap Insertion
When circuit boards are inserted into systems carrying live
supply voltages (“hot swapped”), high inrush currents often
result due to the charging of bulk capacitance that resides
across the circuit board’s supply pins. These current spikes
can cause the system’s supply voltages to temporarily go out
of regulation causing data loss or system lock-up. In more
extreme cases, the transients occurring during a hot swap
event may cause permanent damage to connectors or on-
board components.
The MIC2589 and the MIC2595 are designed to address
these issues by limiting the maximum current, which is
allowed to flow during hot swap events. This is achieved by
implementing a constant-current loop at turn-on. In addition
to inrush current control, the MIC2589 and the MIC2595
incorporate input voltage supervisory functions and user-
programmable overcurrent protection, thereby providing ro-
bust protection for both the system and the circuit board.
Start-Up Cycle
When the input voltage is to the IC is between the overvoltage
and undervoltage thresholds (MIC2589 and MIC2589R) or is
greater than V
initiated. When the IC is enabled, the GATE pin voltage rises
from 0V with respect to V
This 10V gate drive is sufficient to fully enhance commonly
available power MOSFETs for the lowest possible DC losses.
Capacitor C
while R4 minimizes the potential for high frequency parasitic
oscillations from occurring in M1. The drain current of the
MOSFET is regulated to ensure that it never exceeds the
programmed threshold, as described in the “Circuit Breaker
Function” section.
Capacitor C
delay, t
must last to signal a fault condition and to cause an output
latch-off. These devices will be driving a capacitive load in
most applications, so a properly chosen value of C
prevents false-, or nuisance-, tripping at turn-on as well as
providing immunity to noise spikes after the start-up cycle is
complete. The procedure for selecting a value for C
given in the “Circuit Breaker Function” section.
Resistor R4, in series with the power MOSFET’s gate, may be
required in some layouts to minimize the potential for para-
sitic oscillations occurring in M1. Note though, that resistance
in this device of the circuit has a slight destabilizing effect
upon the MIC2589/95’s current regulation loop. If possible,
use high-frequency PCB layout techniques and use a dummy
resistor, such that R4 = 0 . If during prototyping an R4 is
required, common values for R4 range between 4.7 to 20
for various power MOSFETs.
March 2004
MIC2589/2595
FLT
, which is the time for which an overcurrent event
GATE
FILTER
ON
(MIC2595 and MIC2595R), a start cycle is
compensates circuitry internal to the IC,
sets the value of overcurrent detector
EE
to approximately 10V above V
FILTER
FILTER
EE
is
.
11
The Power-Good Output Signals
For the MIC2589/95-1 and MIC2589R/95R-1, power-good
output signal PWRGD1 will be high impedance when V
drops below V
V
MIC2589R/95R-2, power-good output signal /PWRGD1 will
pull down to the potential of the V
drops below V
is above V
PWRGD
output. PWRGD
signal for one or more following DC/DC converter modules or
for other system uses as desired. When used as an enable
signal, the time necessary for the PWRGD (or /PWRGD)
signal to pull-up (when in high impedance state) will depend
upon the load (RC) that is present on this output.
Power-good output signals PWRGD2 (/PWRGD2) and
PWRGD3 (/PWRGD3) follow the assertion of PWRGD1
(/PWRGD1) with a sequencing delay set by an external
capacitor (C
V
PWRGD2 and PWRGD1 is given by:
where V
threshold voltage for PGTIMER and I
cally) is the internal PGTIMER charge current. Similarly, an
expression for the sequencing delay between PWRGD3 and
PWRGD2 is given by:
where V
threshold voltage for PGTIMER. Therefore, power-good out-
put signal PWRGD2 (/PWRGD2) will be delayed after the
assertion of PWRGD1 (/PWRGD1) by:
Power-good output signal PWRGD3 (/PWRGD3) follows the
assertion of PWRGD2 by a delay:
For example, for a 10 F value for C
signal PWRGD2 will be asserted 140ms after PWRGD1.
Power-good signal PWRGD3 will then be asserted 140ms
after PWRGD2 and 255ms after the assertion of PWRGD1.
The relationships between V
PWRGD2, and PWRGD3 are shown in Figure 6.
DRAIN
EE
. An expression for the sequencing delay between
t
PGDLY3 2
t
t
t
PGDLY2-1
PGDLY3-2
PGDLY2 1
is above V
X
THRESH(PG2)
THRESH(PG3)
signal and the -2 parts have an active-low /PWRGD
PGTH
PG
PGTH
) from the controller’s PGTIMER pin (Pin 2) to
PGTH
(ms)
(ms)
. Hence, the -1 parts have an active-high
X
(or /PWRGD
V
V
and will be high impedance when V
THRESH(PG3)
PGTH
THRESH(PG2)
, and will pull-down to V
(= 0.63V, typically) is the PWRGD2
(= 1.15V, typically) is the PWRGD3
14
11.5
I
PGTIMER
. For the MIC2589/95-2 and the
C
PG
C
X
PG
) may be used as an enable
I
DRAIN
( F) ms
PGTIMER
– V
( F) ms
C
DRAIN
THRESH(PG2)
PG
PG
PGTIMER
, V
, power-good output
PGTH
pin when V
(= 45 A, typi-
, PWRGD1,
DRAIN
M9999-031504
C
PG
Micrel
DRAIN
DRAIN
DRAIN
when
X