AD8325-EVAL Analog Devices, AD8325-EVAL Datasheet - Page 4

• Manufacturer Part Number: AD8325-EVAL
• Description: 5 V CATV Line Driver Fine Step Output Power Control
• Manufacturer: Analog Devices

ABSOLUTE MAXIMUM RATINGS
Supply Voltage +V
Input Voltages
Internal Power Dissipation
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C
AD8325
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8325 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Pin No.
1
2
3
4, 8, 11, 12,
13, 16, 17, 18,
22, 24, 28
5, 9, 10, 19,
20, 23, 27
6
7
14
15
21
25
26
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Pins 5, 9, 10, 19, 20, 23, 27 . . . . . . . . . . . . . . . . . . . . . . 6 V
Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.5 V
Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W
Model
AD8325ARU
AD8325ARU-REEL
AD8325-EVAL
Thermal Resistance measured on SEMI standard 4-layer board.
Mnemonic
DATEN
SDATA
CLK
GND
V
TXEN
SLEEP
OUT–
OUT+
BYP
V
V
S
CC
IN+
IN–
Temperature Range
–40°C to +85°C
–40°C to +85°C
Description
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic
0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta-
neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the
internal register with the MSB (Most Significant Bit) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.
Common External Ground Reference.
Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.
Logic “0” disables transmission. Logic “1” enables transmission.
Low Power Sleep Mode. Logic 0 enables Sleep mode, where Z
current is reduced to 4 mA. Logic 1 enables normal operation.
Negative Output Signal.
Positive Output Signal.
Internal Bypass. This pin must be externally ac-coupled (0.1 µF cap).
Noninverting Input. DC-biased to approximately V
capacitor.
Inverting Input. DC-biased to approximately V
PIN FUNCTION DESCRIPTIONS
ORDERING GUIDE
Package Description
28-Lead TSSOP
28-Lead TSSOP
Evaluation Board
CC
/2. Should be ac-coupled with a 0.1 µF capacitor.
CC
DATEN
SDATA
SLEEP
PIN CONFIGURATION
TXEN
OUT–
GND
GND
GND
GND
GND
/2. Should be ac-coupled with a 0.1 µF
CLK
V
V
V
CC
CC
CC
67.7°C/W
67.7°C/W
JA
10
11
12
13
14
1
2
3
4
5
6
7
8
9
(Not to Scale)
TOP VIEW
AD8325
OUT
goes to 400 Ω and supply
WARNING!
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
V
V
V
GND
V
GND
BYP
V
V
GND
GND
GND
OUT+
CC
IN–
IN+
CC
CC
CC
Package Option
RU-28
RU-28
ESD SENSITIVE DEVICE