AD8328 Analog Devices, AD8328 Datasheet - Page 7

• Manufacturer Part Number: AD8328
• Description: 5 V Upstream Cable Line Driver
• Manufacturer: Analog Devices

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. 20-Lead QSOP and 20-Lead LFCSP Pin Function Descriptions
Pin No.
20-Lead
QSOP
1, 3, 4, 7,
11, 20
2, 19
5
6
8
9
10
12
13
14
15
16
17
18
Pin No.
20-Lead
LFCSP
1, 2, 5, 9,
18, 19
17, 20
3
4
6
7
8
10
11
12
13
14
15
16
Figure 5. 20-Lead QSOP Pin Configuration
DATEN
SDATA
GND
GND
GND
V
V
GND
V
CLK
IN+
IN–
CC
Mnemonic
GND
V
V
V
DATEN
SDATA
CLK
SLEEP
NC
BYP
V
V
RAMP
TXEN
CC
IN+
IN−
OUT−
OUT+
10
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
(Not to Scale)
AD8328
TOP VIEW
Description
Common External Ground Reference.
Common Positive External Supply Voltage. A 0.1 μF capacitor must decouple each pin.
Noninverting Input. DC-biased to approximately V
Inverting Input. DC-biased to approximately V
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register.
A Logic 0-to-Logic 1 transition transfers the latched data to the attenuator core (updates the gain)
and simultaneously inhibits serial data transfer into the register.
A Logic 1-to-Logic 0 transition inhibits the data latch (holds the previous gain state) and
simultaneously enables the register for serial data load.
Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the
internal register with the most significant bit (MSB) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit
master-slave register.
A Logic 0-to-Logic 1 transition latches the data bit, and a Logic 1-to-Logic 0 transfers the data bit
to the slave. This requires the input serial data-word to be valid at or before this clock transition.
Low Power Sleep Mode. In the sleep mode, the AD8328’s supply current is reduced to 20 μA.
A Logic 0 powers down the part (high Z
No Connect.
Internal Bypass. This pin must be externally ac-coupled (0.1 μF capacitor).
Negative Output Signal
Positive Output Signal
External RAMP Capacitor (Optional)
Logic 0 Disables Forward Transmission. Logic 1 enables forward transmission.
20
19
18
17
16
15
14
13
12
11
V
TXEN
RAMP
V
V
BYP
NC
SLEEP
GND
GND
CC
OUT+
OUT–
Rev. A | Page 7 of 20
OUT
state), and a Logic 1 powers up the part.
CC
/2. Should be ac-coupled with a 0.1 μF capacitor.
CC
Figure 6. 20-Lead LFCSP Pin Configuration
/2. Should be ac-coupled with a 0.1 μF capacitor.
GND
GND
GND
V
V
IN+
IN–
1
2
3
4
5
20 19 18
6
(Not to Scale)
AD8328
TOP VIEW
7
8
17
9
16
10
15
14
13
12
11
RAMP
BYP
NC
V
V
OUT+
OUT–
AD8328