AD8343 Analog Devices, AD8343 Datasheet - Page 17

• Manufacturer Part Number: AD8343
• Description: DC-to-2.5 GHz High IP3 Active Mixer
• Manufacturer: Analog Devices

The plotted stability circles in Figure 14 indicate that the guiding
principle for preventing stability problems due to common-mode
output loading is to avoid high-Q common-mode inductive load-
ing. This stability concern is of particular importance when the
output is taken from the device with a center-tapped transformer.
The common-mode inductance to the center tap, which arises
from imperfect coupling between the halves of the primary wind-
ing, produces an unstable common-mode loading condition.
Fortunately, there is a simple solution: insert a ferrite bead in
series with the center tap, then provide effective RF bypassing on
the power supply side of the bead. The bead should develop sub-
stantial impedance (tens of ohms) by the time a frequency of about
200 MHz is reached. The Murata BLM21P300S is a possible
choice for many applications.
FREQUENCY: 50MHz TO 2500MHz
FREQUENCY: 50MHz TO 2500MHz
150MHz
50MHz
INCREMENT: 100MHz
INCREMENT: 100MHz
50MHz
150MHz
In cases where a transmission line balun is used at the output,
the solution needs more exploration. After the differential imped-
ance matching network is designed, it is possible to measure
or simulate the common-mode impedance seen by the device.
This impedance should be plotted against the stability circles to
ensure stable operation. An alternate topology for the matching
network may be required if the proposed network produces an
unacceptable common-mode impedance.
For the device input, capacitive common-mode loading produces
an unstable circuit, particularly at low frequencies (Figure 13).
Fortunately, either type of single-ended-to-differential conver-
sion (transmission line balun or flux-coupled transformer) tends
to produce inductive loading, although some matching network
topologies and/or component values could circumvent this
desirable behavior. In general, a simulation of the common-mode
termination seen by the AD8343’s input port should be plotted
against the input stability circles to check stability. This is especially
recommended if the single-ended-to-differential conversion is done
with a discrete component circuit.
LO Input Interface (LOIP, LOIM)
The LO terminals of the AD8343 are internally biased; connec-
tions to these terminals should include dc blocks, except as
noted below in the DC Coupling the LO section.
The differential LO input return loss (re 50 Ω is presented in
Figure 16. As shown, this port has a typical differential return
loss of better than 9.5 dB (2:1 VSWR). If better return loss is
desired for this port, differential matching techniques can also
be applied.
VPOS
S PARAMETER TEST SET
ATN-4111B
NETWORK ANALYZER
1nH
HP8753C
BIAS
TEE
0.1 F
0.1 F
BIAS
TEE
1
2
3
4
5
6
7
BIAS
TEE
COMM
INPP
INPM
DCPL
VPOS
PWDN
COMM
AD8343
BIAS
TEE
HP-IB
COMM
COMM
COMM
OUTM
OUTP
LOIM
LOIP
14
13
12
11
10
9
8
ATN-4000 SERIES
TEST SYSTEM
MULTIPORT
AD8343