AD8364-EVAL Analog Devices, AD8364-EVAL Datasheet - Page 16

• Manufacturer Part Number: AD8364-EVAL
• Description: LF to 2.7GHz, Dual 60dB TruPwr Detector
• Manufacturer: Analog Devices

PRELIMINARY TECHNICAL DATA
GENERAL DESCRIPTION AND THEORY
The AD8364 is a dual channel 2.7GHz true RMS responding
detector with 60 dB measurement range and incorporates two
AD8362 channels with shared reference circuitry (See the
AD8362 datasheet for more information). Multiple enhancements
have been made to the AD8362 cores to improve measurement
accuracy. Log-conformance peak-to-peak ripple has been
reduced to < ±0.2 dB, over the entire dynamic range.
Temperature stability of the RMS output measurements provides
< ± 0.5 dB error over the specified temperature range of -40
85
channels offers extremely temperature stable channel difference
outputs at OUTP and OUTN. Given well matched channels
through IC integration, the RMS measurement outputs, OUTA
and OUTB, will drift in the same manner (<± 0.5 dB). With
OUTP shorted to FBKA, the function at OUTP is:
When OUTN is shorted to FBKB, the function at OUTN is:
The difference outputs, OUTP and OUTN, are insensitive to the
common drift due to the difference cancellation of OUTA and
OUTB.
The AD8364 is a fully calibrated RMS-to-DC converter capable
of operation from signals as low as a few Hertz to at least 2.7GHz.
Unlike logarithmic amplifiers, the AD8364 response is waveform
independent. The device accurately measures waveforms having
a high peak-to-rms ratio (crest factor). A block diagram is shown
below in figure 29.
A single channel of the AD8364 consists of a high performance
AGC loop. Referring to figure 30, the AGC loop is comprised of
a wide bandwidth variable gain amplifier (VGA), square law
detectors, Amplitude Target circuit, and output driver.
detailed description of the functional blocks, see AD8362 data sheet.
o
C, through proprietary techniques. The use of well matched
PWDN
COMR
VPSA
VPSB
INHA
INHB
INLA
INLB
OUTN = OUTB – OUTA + VLVL
2
2
3
OUTP = OUTA – OUTB + VLVL
2
2
3
3
25
6
7
8
9
2
0
1
CHPB
CHPA
24
1
TruPwr™
TruPwr™
Channel B
Channel A
DECB
DECA
Figure 29. Block Diagram
23
2
COMB
COMA VPSR ACOM TEMP ACOM CLPA
22
3
OUTA
OUTB
ADJB ADJA
BIAS
21
4
20
5
V2I
TEMP
VREF VLVL CLPB
19
6
18
7
V2I
17
8
16
15
14
13
22
11
10
9
OUTA
OUTP
OUTN
OUTB
VSTA
FBKA
FBKB
VSTB
For more
Rev. PrC Ι Page 16 of 23
(1)
(2)
o
C to
Square Law Detector and Amplitude Target
The output of the VGA, called V
square law detector. The detector provides the true RMS
response of the RF input signal, independent of waveform,
up to crest factors of 6. The detector output, called I
fluctuating current with positive mean value. The difference
between I
integrated by C
is the on chip 25pF filter capacitor. CLP[A,B] can be used
to arbitrarily increase the averaging time while trading off
response time. When the AGC loop is at equilibrium:
This equilibrium occurs only when:
Where V
Since the square law detectors are electrically identical and
well matched, process and temperature-dependant variations
are effectively cancelled.
By forcing the above identity through varying the VGA set-
point, it is apparent that:
Substituting the value of V
When connected as a measurement device VST[A,B] =
OUT[A,B]. Solving for OUT[A,B] as a function of RF
Where V
the intercept voltage, since Log10(1) = 0 when RMS(RF
V
Z
. If desired, the effective value of V
INH[A,B]
INL[A,B]
CHP[A,B]
VST[A,B]
RMS(V
VREF
TGT
SLOPE
OUT[A,B] = V
MEAN(V
V
SQU
RMS(G
ST[A,B]
SIG
V
Offset –
Nulling
MEAN(I
V
2.5V
REF
is an attenuated version of the V
IN
) = √(MEAN(V
and an internally generated current, I
is approximately1V/decade or 50mV/dB. V
-28 to +40dB
F
VGA
Set-Point
Interface
Band-Gap
Reference
and a capacitor attached to CLP[A,B]. C
Figure 30. Single Channel Details
0
*RF
G
SIG
SET
SQU
2
) = V
IN
V
) = I
SIG
SLOPE
CLP[A,B]
exp(-V
SIG
x
I
C
external
Matched Wide
Band Squarers
TGT[A,B]
SQU
2
TGT[A,B]
LPF
*Log10(RMS(RF
SIG
, we have:
(6)
(7)
2
)) = √(V
ST[A,B]
SIG
I
2
TGT
, is applied to a wideband
x
2
C
/V
V
F
SLOPE
AmplitudeTarget
for V
REF
AD8364
Internal resistors
set buffer gain to 5
GNS
(3)
TGT
SIG
Output
Buffer
(4)
Temperature
Compensation
)) = V
may be altered by
2
) = V
REF
IN
V
)/V
OUT[A,B]
voltage.
TGT
TGT
Z
TGT[A,B]
)
SQU
IN
OUT[A,B]
ACOM
ADJ[A,B]
(5)
, is a
:
IN
,is
) =
Z
is
F