IDT72V263L10PFI IDT, Integrated Device Technology Inc, IDT72V263L10PFI Datasheet - Page 31
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
IDT72V263L10PFI
Manufacturer Part Number
IDT72V263L10PFI
Description
IC FIFO 8192X18 10NS 80QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V293L7-5PF.pdf
(45 pages)
Specifications of IDT72V263L10PFI
Function
Asynchronous, Synchronous
Memory Size
144K (8K x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
80-TQFP, 80-VQFP
Configuration
Dual
Density
144Kb
Access Time (max)
6.5ns
Word Size
18/9Bit
Organization
8Kx18/16Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
30@9BIT/35@18BITmA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V263L10PFI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V263L10PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V263L10PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. If the part is empty at the point of Retransmit, the Empty Flag (EF) will be updated based on RCLK (Retransmit clock cycle). Valid data will also appear on the output.
2. OE = LOW: enables data to be read on outputs Q
3. W
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
5. There must be at least two words written to and read from the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
Q
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
WCLK
0
RCLK
WEN
EF
REN
1
PAE
- Q
PAF
= first word written to the FIFO after Master Reset, W
HF
RT
If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263,
16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384
for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293.
(1)
n
t
ENS
W
x
t
A
t
ENS
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
W
t
RTS
0
-Q
x+1
n
.
2
= second word written to the FIFO after Master Reset.
1
t
A
t
t
ENH
HF
t
SKEW2
1
W
1
TM
(3)
31
NARROW BUS FIFO
2
t
PAFS
TM
2
NARROW BUS FIFO
t
A
W
2
(3)
3
t
PAES
t
A
COMMERCIAL AND INDUSTRIAL
W
TEMPERATURE RANGES
3
(3)
FEBRUARY 11, 2009
t
t
A
ENH
4666 drw16
W
4