AD8555AR-EVAL Analog Devices, AD8555AR-EVAL Datasheet - Page 26

• Manufacturer Part Number: AD8555AR-EVAL
• Description: Zero-Drift, Single-Supply, Sensor Signal Amplifier with Digitally Programmable Gain and Offset
• Manufacturer: Analog Devices

AD8555
RF INTERFERENCE
All instrumentation amplifiers show dc offset as the result of
rectification of high frequency out-of-band signals that appear
at their inputs. The circuit in Figure 59 provides good RFI sup-
pression without reducing performance within the AD8555 pass
band. Resistor R1 and Capacitor C1, and likewise Resistor R2
and Capacitor C2, form a low-pass RC filter that has a −3 dB
bandwidth equal to f
R1, R2 and C1, C2 form a bridge circuit whose output appears
across the amplifier’s input pins. Any mismatch between C1, C2
unbalances the bridge and reduce the common-mode rejection.
Using the component values shown, this filter has a bandwidth
of approximately 40 kHz. To preserve common-mode rejection
in the AD8555’s pass band, capacitors need to be 5% (silver
mica) or better and should be placed as close to its inputs as
possible. Resistors should be 1% metal film. Capacitor C3 is
60
50
40
30
20
10
0
0.1
V
S
= ±2.5V
Figure 58. Negative Overshoot Graph vs. C
R
R
S
S
(−3 dB)
= 100
LOAD CAPACITANCE (nF)
1.0
C
L
= 1/2 π × R1 × C1. It can be seen that
100Ω
100Ω
VDD
0
10.0
100Ω
100Ω
Figure 60. A Single-Supply Data Acquisition Circuit Using the AD8555
R
R
S
S
= 20
= 10
R
S
10nF
= 50
S
L
DIGIN
R
S
= 0
100.0
1
2
3
4
VDD
FILT/DIGOUT
DIGIN
VNEG
Rev. 0 | Page 26 of 28
AD8555
VCLAMP
VOUT
VPOS
VSS
needed to maintain common-mode rejection at low frequencies.
This introduces a second low-pass network, R1 + R2 and C3
that has a −3 dB frequency equal to 1/(2 π × (R1 + R2)(C3)).
This circuit’s −3 dB signal bandwidth is approximately 4 kHz
when a C3 value of 0.047 µF is used (see Figure 59).
SINGLE-SUPPLY DATA ACQUISITION SYSTEM
Interfacing bipolar signals to single-supply analog-to-digital
converters (ADCs) presents a challenge. The bipolar signal must
be mapped into the input range of the ADC. Figure 60 shows
how this translation can be achieved. The output offset can be
programmed to a desirable level to accommodate the input
voltage requirement of the ADC.
8
7
6
5
VNEG
VPOS
VDD
4.02kΩ
4.02kΩ
0.047µF
R2
R1
2
C3
AIN
V
4
DD
Figure 59. RFI Suppression Method
AD7476
12 BIT
VDD
C2
1nF
1
2
3
4
VDD
FILT/DIGOUT
DIGIN
VNEG
AD8555
VCLAMP
VOUT
VPOS
VSS
8
7
6
5
1nF
C1
VSS
VDD