IDT72V845L15PFI IDT, Integrated Device Technology Inc, IDT72V845L15PFI Datasheet - Page 22
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IDT72V845L15PFI
Manufacturer Part Number
IDT72V845L15PFI
Description
IC FIFO SYNC 4096X18 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V805L20PF8.pdf
(26 pages)
Specifications of IDT72V845L15PFI
Function
Asynchronous, Synchronous
Memory Size
72K (4K x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Configuration
Quad
Density
144Kb
Access Time (max)
10ns
Word Size
18b
Organization
4Kx18x2
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Bi-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
60mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V845L15PFI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V845L15PFI
Manufacturer:
IDT
Quantity:
221
Company:
Part Number:
IDT72V845L15PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V845L15PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
NOTES:
1. t
2. LD = HIGH, OE = LOW
3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.
Q
D
D
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
Q
WCLK
RCLK
0
0
0
edge of WCLK and the rising edge of RCLK is less than t
rising edge of RCLK is less than t
WEN
SKEW1
0
SKEW1
REN
-
-
WCLK
RCLK
-
Q
D
-
OE
WEN
EF
REN
17
17
Q
D
OR
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus t
is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and the
17
17
t
ENS
t
DS
t
t
OLZ
Figure 27. OR
ENS
Figure 26. Read Cycle Timing with Double Register-Buffered EF
W
SKEW1
t
ENH
1
DATA IN OUTPUT REGISTER
t
A
, then the OR deassertion may be delayed one extra RCLK cycle.
t
REF
OR
OR
OR Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)
t
OR
OE
t
DH
NO OPERATION
t
FIRST WORD
ENH
t
t
t
ENS
SKEW1
DS
1
SKEW1
W
2
. then the EF deassertion may be delayed an extra RCLK cycle.
(1)
t
t
SKEW1
DH
t
(1)
ENH
1
2
W
3
22
LAST WORD
3
W
t
4
t
REF
A
EF EF
EF EF (IDT Standard Timing)
t
DS
t
OHZ
2
t
REF
W
COMMERCIAL AND INDUSTRIAL
t
[n +2]
CLKH
t
REF
W
TEMPERATURE RANGES
1
t
CLK
REF
. If the time between the rising
FEBRUARY 11, 2009
W
t
CLKL
[n+3]
4295 drw 26
4295 drw 27