IDT72V851L10PFG IDT, Integrated Device Technology Inc, IDT72V851L10PFG Datasheet - Page 7

• Manufacturer Part Number: IDT72V851L10PFG
• Description: IC FIFO SYNC 4096X18 10NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V851L10PFG

• Function: Asynchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Quad
• Density: 144Kb
• Access Time (max): 6.5ns
• Word Size: 9b
• Organization: 8Kx9x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 72V851L10PFG

contains four 8-bit offset registers which can be loaded with data on the inputs,
or read on the outputs. See Figure 3 for details of the size of the registers and
the default values.
(WENB1) and WENA2/LDA (WENB2/LDB) are set LOW, data on the DA (DB)
inputs are written into the Empty (Least Significant Bit) Offset register on the first
LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the
Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH
transition of WCLKA (WCLKB), into the Full (Least Significant Bit) Offset register
on the third transition, and into the Full (Most Significant Bit) Offset register on
the fourth transition. The fifth transition of WCLKA (WCLKB) again writes to the
Empty (Least Significant Bit) Offset register.
8
8
8
8
8
8
8
8
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
If FIFO A (B) is configured to have programmable flags, when the WENA1
7
7
7
7
72V801 - 256 x 9 x 2
72V831 - 2,048 x 9 x 2
Empty Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
Empty Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
2
2
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
(MSB)
(MSB)
000
000
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
7
7
7
7
72V811 - 512 x 9 x 2
72V841 - 4,096 x 9 x 2
Default Value 007H
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Full Offset (LSB)
Full Offset (LSB)
7
or two offset registers can be written and then by bringing LDA (LDB) HIGH,
FIFO A (B) is returned to normal read/write operation. When LDA (LDB) is set
LOW, and WENA1 (WENB1) is LOW, the next offset register in sequence is
written.
WENA2/LDA (WENB2/LDB) is set LOW and both Read Enables RENA1,
RENA2 (RENB1, RENB2) are set LOW. Data can be read on the LOW-to-HIGH
transition of the Read Clock RCLKA (RCLKB).
registers.
3
3
However, writing all offset registers does not have to occur at one time. One
The contents of the offset registers can be read on the QA (QB) outputs when
A read and write should not be performed simultaneously to the offset
(MSB)
(MSB)
0000
0000
TM
1
1
(MSB)
(MSB)
0
0
0
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
7
7
7
7
72V821 - 1,024 x 9 x 2
72V851 - 8,192 x 9 x 2
COMMERCIAL AND INDUSTRIAL
Empty Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Full Offset (LSB)
TEMPERATURE RANGES
4
4
OCTOBER 22, 2008
(MSB)
00000
(MSB)
00000
1
1
(MSB)
(MSB)
4093 drw 05
00
00
0
0
0
0
0
0
0
0