IDT72V851L15PFI IDT, Integrated Device Technology Inc, IDT72V851L15PFI Datasheet - Page 10

• Manufacturer Part Number: IDT72V851L15PFI
• Description: IC FIFO SYNC 4096X18 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V851L15PFI

• Function: Asynchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Quad
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 8Kx9x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 40mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V851L15PFI

NOTE:
1. t
WENA2 (WENB2)
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
NOTE:
1. When t
WENA1 (WENB1)
WENA2 (WENB2)
(RENB1, RENB2)
WCLKA, WCLKB
(RENB1, RENB2)
RCLKA (RCLKB)
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than t
edge.
SKEW1
When
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
RENA1, RENA2
RENA1, RENA2
(If Applicable)
(QB
(DB
(QB
OEA (OEB)
t
is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
OEA (OEB)
SKEW1
SKEW1
EFA (EFB)
QA
DA
EFA (EFB)
QA
(WCLKB)
(WENB1)
(RCLKB)
0
WCLKA
0
0
WENA1
0
RCLKA
0
0
- QB
- DB
- QB
- QA
≥ minimum specification, t
< minimum specification, t
- DA
- QA
8
8
8
8
8
)
)
8
)
t
ENS
FRL
FRL
t
= 2t
= t
ENS
CLK
t
ENS
CLK
t
OLZ
+ t
+ t
t
DS
t
SKEW1
SKEW1
SKEW1
t
ENH
t
CLKH
Figure 7. First Data Word Latency Timing
or t
t
REF
t
CLK
A
t
OE
+ t
Figure 6. Read Cycle Timing
SKEW1
D
t
CLK
0
(First Valid
NO OPERATION
t
SKEW1
t
t
OLZ
t
FRL
REF
10
t
CLKL
(1)
(1)
VALID DATA
t
t
ENS
OHZ
D
SKEW1
1
TM
t
OE
, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
t
A
t
REF
D
2
COMMERCIAL AND INDUSTRIAL
D
0
t
A
TEMPERATURE RANGES
OCTOBER 22, 2008
D
3
4093 drw 08
D
4093 drw 09
1