IDT72V275L15PFGI8 IDT, Integrated Device Technology Inc, IDT72V275L15PFGI8 Datasheet - Page 13
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
IDT72V275L15PFGI8
Manufacturer Part Number
IDT72V275L15PFGI8
Description
IC FIFO SS 32768X18 15NS 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V275L15TF8.pdf
(25 pages)
Specifications of IDT72V275L15PFGI8
Function
Synchronous
Memory Size
589K (32K x 18)
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
576Kb
Access Time (max)
10ns
Word Size
18b
Organization
32Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
60mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Lead Free Status / Rohs Status
Compliant
Other names
72V275L15PFGI8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V275L15PFGI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
PROGRAMMABLE ALMOST-FULL FLAG (PAF
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The PAF will go LOW after (32,768-m) writes for the IDT72V275
and (65,536-m) writes for the IDT72V285. The offset “m” is the full offset value.
The default setting for this value is stated in the footnote of Table 1.
IDT72V275 and (65,537-m) writes for the IDT72V285, where m is the full offset
value. The default setting for this value is stated in the footnote of Table 2.
and FWFT Mode), for the relevant timing information.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
in the FIFO. The default setting for this value is stated in the footnote of Table 2.
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
In FWFT mode, the PAF will go LOW after (32,769-m) writes for the
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
PAF is synchronous and updated on the rising edge of WCLK.
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
In FWFT mode, the PAE will go LOW when there are n+1 words or less
PAF
PAF
PAF)
PAF
PAE
PAE
PAE
PAE)
TM
13
and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF
beyond half-full sets HF LOW. The flag remains LOW until the difference
between the write and read pointers becomes less than or equal to half of the
total depth of the device; the rising RCLK edge that accomplishes this condition
sets HF HIGH.
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 32,768
for the IDT72V275 and 65,536 for the IDT72V285.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 32,769 for the
IDT72V275 and 65,537 for the IDT72V285.
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Standard
PAE is synchronous and updated on the rising edge of RCLK.
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
In IDT Standard mode, if no reads are performed after reset (MRS or
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
- Q
17
) are data outputs for 18-bit wide data.
0
HF
HF
HF)
HF
-Q
17
)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES