IDT72V265LA15TF IDT, Integrated Device Technology Inc, IDT72V265LA15TF Datasheet - Page 17
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IDT72V265LA15TF
Manufacturer Part Number
IDT72V265LA15TF
Description
IC FIFO SS 16384X18 15NS 64STQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V255LA10TFG.pdf
(27 pages)
Specifications of IDT72V265LA15TF
Function
Synchronous
Memory Size
288K (16K x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-STQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V265LA15TF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V265LA15TF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V265LA15TF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V265LA15TFGI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V265LA15TFGI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V265LA15TFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH
NOTES:
1. t
2. LD = HIGH.
3. First word latency: 60ns + t
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
Q
Q
D
D
8,192 x 18, 16,384 x 18
WCLK
RCLK
0
0
WCLK
0
0
WEN
RCLK
rising edge of the RCLK and the rising edge of the WCLK is less than t
REN
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
- Q
- D
WEN
SKEW3
REN
- D
- Q
OE
EF
n
n
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
t
ENS
t
DATA IN OUTPUT REGISTER
ENS
t
t
OLZ
t
SKEW1
ENH
t
REF
t
A
REF
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
t
OE
(1)
+ 1*
TRCLK
t
SKEW3
t
t
ENH
ENS
t
DS
t
.
A
D
(1)
1
0
NO WRITE
NO OPERATION
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
t
t
DHS
ENH
LAST WORD
1
SKEW3
2
t
WFF
, then EF deassertion may be delayed one extra RCLK cycle.
SKEW1
t
t
OHZ
t
DS
t
DS
ENS
t
CLKH
, then the FF deassertion may be delayed one extra WCLK cycle.
D
D
1
NO OPERATION
X
t
WFF
t
t
ENH
DH
DATA READ
17
t
DH
t
CLK
2
t
CLKL
t
CLKH
t
t
REF
ENS
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
ENS
t
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
WFF
2
REF
TEMPERATURE RANGES
). If the time between the
). If the time between the
NEXT DATA READ
t
t
ENS
WFF
OCTOBER 22, 2008
t
DS
D
0
D
X
+1
t
REF
t
t
ENH
A
4672 drw 10
t
DH
t
WFF
4672 drw 11
D
1