SN7325 Si-En, SN7325 Datasheet - Page 9

• Manufacturer Part Number: SN7325
• Description: Multi Function I/O Driver
• Manufacturer: Si-En

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Detailed Description
Functional Overview
The SN7325 is a Multi-function I/O driver operating
from a +2.4V to 5.5V supply with eight push-pull and
eight open-drain I/O ports. Each open-drain and
push-pull port is rated to sink 20mA at 0.26V headroom,
and the entire device is rated to sink 320mA at 0.26V
headroom into all ports combined. The outputs drive
loads connected to supplies up to +5.5V.
The SN7325 is set to four I
address select inputs AD0 and AD1, and is accessed over
an I
clears the serial interface in case of a bus lockup,
terminating any serial transaction to or from the SN7325.
The SN7325 consists of input, output port registers,
configuration registers and interrupt control register. All
I/O ports offer latching transition detection when
configured as inputs. All input ports are continuously
monitored for changes.
A latching interrupt output, INT
logic changes on ports used as inputs. Data changes on
any input port forces INT
I/O port level through the serial interface does not cause
an interrupt. The interrupt output INT
successfully by reading the corresponding input/output
ports.
Ports default to logic-high or logic-low on power-up in
groups of four (see Table 1).
Initial Power-Up
On power-up, the transition detection logic is reset, and
_______
INT
ports are set according to the I2C slave address selection
inputs, AD0 and AD1 (see Table 1). For I/O ports used as
inputs, ensure that the default states are logic-high so that
the I/O ports power up in the high impedance state.
Power-On Reset
The SN7325 contains an integral power-on-reset (POR)
circuit that ensures all registers are reset to a known state
on power-up. When VCC rises above VPOR (2.3V max),
the POR circuit releases the registers and 2-wire interface
for normal operation. When VCC drops to less than
VPOR, the SN7325 resets all register contents to the
POR defaults.
________
RST
The active-low RST
involving the SN7325, forcing the SN7325 into the I2C
STOP condition. A reset does not affect the interrupt
output.
Standby Mode
When the serial interface is idle, the SN7325
automatically enters standby mode, drawing minimal
supply current.
Jan. 2009, Ver1.0
2
C serial interface up to 400 kHz. The RST
is reset. The power-up default states of the 16 I/O
Input
________
_______
input voids any I2C transaction
to a logic-low. Changing the
2
_______
C slave addresses using the
, is programmed to flag
_______
________
is cleared
input
9
I/O Port Input Transition Detection
All I/O ports configured as inputs are monitored for
changes since the expander was last accessed through the
serial interface. The open-drain interrupt output, INT
activates when one of the port pins changes states and
only when the pin is configured as an input. The interrupt
deactivates when the input/output register is read. A pin
configured as an output does not cause an interrupt. Each
8-bit port register is read independently; therefore, an
interrupt caused by port A (OD0~OD7) is not cleared by
a read of port B (PP0~PP7)’s register.
Changing an I/O from an output to an input may cause a
false interrupt to occur if the state of that I/O does not
match the content of output port register. The SN7325
has interrupt control register to avoid false interrupt by
setting the interrupt control register bit high firstly, when
the I/O state is stable, clear the interrupt control register
to enable the input transition detection function.
Accessing the SN7325
Serial Addressing
The SN7325 operates as a slave that sends and receives
data through a 2-wire interface. The interface uses a
serial data line (SDA) and a serial clock line (SCL) to
achieve bidirectional communication between master(s)
and slave(s). A master, typically a microcontroller,
initiates all data transfers to and from the SN7325, and
generates the SCL clock that synchronizes the data
transfer (see Figure 1).
SDA operates as both an input and an open-drain output.
A pull up resistor, typically 4.7kΩ, is required on SDA.
SCL operates only as an input. A pull up resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a
single-master system has an open-drain SCL output.
Each transmission consists of a START condition sent by
a master, followed by the SN7325’s 7-bit slave addresses
plus R/W bits, 1 or more data bytes, and finally a STOP
condition (see Figure 2).
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from
high to low while SCL is high. When the master has
finished communicating with the slave, the master issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (see Figure 2)
Bit Transfer
One data bit is transferred during each clock pulse. The
data on SDA must remain stable while SCL is high
(Figure 3).
SI-EN technology
SN7325
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